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CDCEL925PW Datasheet(PDF) 6 Page - Texas Instruments |
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CDCEL925PW Datasheet(HTML) 6 Page - Texas Instruments |
6 / 27 page CDCE925 CDCEL925 SCAS847F – JULY 2007 – REVISED MARCH 2010 www.ti.com DEVICE CHARACTERISTICS over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT OVERALL PARAMETER All outputs off, fCLK=27 MHz, All PLLS on 20 IDD Supply current (see Figure 3) fVCO = 135 MHz; fOUT = 27 mA 9 Per PLL MHz CDCE925 VDDOUT = 3.3 V 2 No load, all outputs on, IDDOUT Supply current (see Figure 4 and Figure 5) mA fOUT = 27 MHz CDCEL925 VDDOUT = 1.8 V 1 Power-down current. Every circuit powered IDDPD fIN = 0 MHz, VDD = 1.9 V 30 mA down except SDA/SCL Supply voltage VDD threshold for power-up VPUC 0.85 1.45 V control circuit fVCO VCO frequency range of PLL 80 230 MHz fOUT LVCMOS output frequency CDCE(L)925 VDDOUT = 1.8 V 230 MHz LVCMOS PARAMETER VIK LVCMOS input voltage VDD = 1.7 V; Is = –18 mA –1.2 V II LVCMOS Input current VI = 0 V or VDD; VDD = 1.9 V ±5 mA IIH LVCMOS Input current for S0/S1/S2 VI = VDD; VDD = 1.9 V 5 mA IIL LVCMOS Input current for S0/S1/S2 VI = 0 V; VDD = 1.9 V –4 mA Input capacitance at Xin/Clk VIClk = 0 V or VDD 6 CI Input capacitance at Xout VIXout = 0 V or VDD 2 pF Input capacitance at S0/S1/S2 VIS = 0 V or VDD 3 CDCE925 - LVCMOS PARAMETER FOR VDDOUT = 3.3 V – MODE VDDOUT = 3 V, IOH = –0.1 mA 2.9 VOH LVCMOS high-level output voltage VDDOUT = 3 V, IOH = –8 mA 2.4 V VDDOUT = 3 V, IOH = –12 mA 2.2 VDDOUT = 3 V, IOL = 0.1 mA 0.1 VOL LVCMOS low-level output voltage VDDOUT = 3 V, IOL = 8 mA 0.5 V VDDOUT = 3 V, IOL = 12 mA 0.8 tPLH, tPHL Propagation delay All PLL bypass 3.2 ns tr/tf Rise and fall time VDDOUT = 3.3 V (20%–80%) 0.6 ns 1 PLL switching, Y2-to-Y3 50 70 tjit(cc) Cycle-to-cycle jitter(2) (3) ps 2 PLL switching, Y2-to-Y5 90 130 1 PLL switching, Y2-to-Y3 60 100 tjit(per) Peak-to-peak period jitter(3) ps 2 PLL switching, Y2-to-Y5 100 160 fOUT = 50 MHz; Y1-to-Y3 70 tsk(o) Output skew (4) ps fOUT = 50 MHz; Y2-to-Y5 150 odc Output duty cycle (5) fVCO = 100 MHz; Pdiv = 1 45% 55% CDCE925 – LVCMOS PARAMETER for VDDOUT = 2.5 V – Mode VDDOUT = 2.3 V, IOH = –0.1 mA 2.2 VOH LVCMOS high-level output voltage VDDOUT = 2.3 V, IOH = –6 mA 1.7 V VDDOUT = 2.3 V, IOH = –10 mA 1.6 VDDOUT = 2.3 V, IOL = 0.1 mA 0.1 VOL LVCMOS low-level output voltage VDDOUT = 2.3 V, IOL = 6 mA 0.5 V VDDOUT = 2.3 V, IOL = 10 mA 0.7 tPLH, tPHL Propagation delay All PLL bypass 3.6 ns tr/tf Rise and fall time VDDOUT = 2.5 V (20%–80%) 0.8 ns (1) All typical values are at respective nominal VDD. (2) 10000 cycles. (3) Jitter depends on configuration. Jitter data is for input frequency = 27 MHz, fVCO = 135 MHz, fOUT = 27 MHz. fOUT = 3.072 MHz or input frequency = 27 MHz, fVCO = 108 MHz, fOUT = 27 MHz. fOUT = 16.384 MHz, fOUT = 25 MHz, fOUT = 74.25 MHz, fOUT = 48 MHz (4) The tsk(o) specification is only valid for equal loading of each bank of outputs, and the outputs are generated from the same divider, data sampled on rising edge (tr). (5) odc depends on output rise- and fall time (tr/tf); 6 Submit Documentation Feedback Copyright © 2007–2010, Texas Instruments Incorporated Product Folder Link(s): CDCE925 CDCEL925 |
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