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NCP5359MNR2G Datasheet(PDF) 3 Page - ON Semiconductor |
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NCP5359MNR2G Datasheet(HTML) 3 Page - ON Semiconductor |
3 / 9 page NCP5359 http://onsemi.com 3 Figure 2. Typical Application PWM EN VOUT 4 V to 15 V 10 V to 13.2 V *Option BST VCC VCC EN PWM DRVH DRVL GND GND SW PIN DESCRIPTION SOIC−8 DFN10 Symbol Description 1 1 BST Upper MOSFET Floating Bootstrap Supply Pin 2 2 PWM PWM Input Pin When PWM voltage is higher than 2.2 V, DRVH will set to 1 and DRVL set to 0 When PWM voltage is lower than 0.8 V, DRVL will set to 1 and DRVH set to 0 When 0.8 V < PWM < 2.2 V and SW < 0, DRVL will set to 1 When 0.8 V < PWM < 2.2 V and SW > 0, DRVL will set to 0 3 3 EN Enable Pin When OVP, TSD or UVLO has happened, the gate driver will pull the pin to low 4 4, 5 VCC Connect to Input Power Supply 10 V to 13.2 V 5 6 DRVL Low Side Gate Drive Output 6 7, 8 GND Ground Pin 7 9 SW Switch Node Pin 8 10 DRVH High Side Gate Drive Output |
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