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NCP5388MNR2G Datasheet(PDF) 11 Page - ON Semiconductor |
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NCP5388MNR2G Datasheet(HTML) 11 Page - ON Semiconductor |
11 / 34 page NCP5388 http://onsemi.com 11 ELECTRICAL CHARACTERISTICS (0°C < TA < 70°C; 0°C < TJ < 85°C; 10.8 V < VCC < 13.2 V; All DAC Codes; CVCC = 0.1 mF, FSW = 400 kHz, unless otherwise stated) Parameter Units Max Typ Min Test Conditions Modulators (PWM Comparators) Minimum Pulse Width Fs = 400 kHz − 30 40 ns Magnitude of the PWM Ramp − 1.0 − V 0% Duty Cycle COMP voltage when the PWM outputs remain LO − 1.2 − V 100% Duty Cycle COMP voltage when the PWM outputs remain HI − 2.3 − V Minimum PWM Linear Duty Cycle (Note 1) FS = 400 kHz − 90 − % PWM Comparator Offset Mismatch (Note 1) Between any 2 phases, FS = 400 kHz − − 40 mV Phase Angle Error Between adjacent phases, FS = 400 kHz −15 − 15 ° Propagation Delay (Note 1) Ramp/Comp crossing to Gx high − 20 − ns Propagation Delay (Note 1) Ramp/Comp crossing to Gx low − 20 − ns PWM Outputs Output High Voltage Sourcing 500 mA 3.3 4.0 4.7 V Output Low Voltage Sinking 500 mA − 25 100 mV Rise Time CL = 20 pF, DVo = 0.3 to 2.0 V − 10 − ns Fall Time CL = 20 pF, DVo = Vmax to 0.7 V − 10 − ns Output Impedance – LO State Resistance to GND (Gx = LO) − 50 − W G4 Gate Pin Source Current during Phase Detect − 70 − mA Phase Detection Period − 50 − ms G4 Phase Detect Threshold Resistance − − 1.0 kW Gate Driver Enable (DRVON) Output High Voltage Sourcing 500 mA 4.0 5.3 5.5 V Output Low Voltage Sinking 500 mA − 50 200 mV Rise Time CL (PCB) = 20 pF, DVo = 10% to 90% − 25 − ns Fall Time CL (PCB) = 20 pF, DVo = 10% to 90% − 25 − ns Internal Pulldown Resistance VCC < UVLO Threshold − 70 140 kW 1. Guaranteed by design. Not tested in production. |
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