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SN65LVDS049 Datasheet(PDF) 5 Page - Texas Instruments |
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SN65LVDS049 Datasheet(HTML) 5 Page - Texas Instruments |
5 / 14 page www.ti.com SN65LVDS049 SLLS575 – AUGUST 2003 SWITCHING CHARACTERISTICS over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT LVDS Outputs (DOUT+, DOUT-) tPLHD Differential propagation delay low to high RL = 100 Ω, 1.3 2.0 ns CL = 15 pF distributed, tPHLD Differential propagation delay high to low 1.4 2.0 ns See Figure 2 tsk(p) Differential pulse skew (|tPHL - tPLH|) 0 0.15 0.4 ns tsk(o) Differential channel-to-channel skew (2) 0 0.05 0.5 ns tsk(pp) Differential part-to-part skew (3) 0 1 ns tr Differential rise time 0.2 0.5 1 ns tf Differential fall time 0.2 0.5 1 ns tPHZ Disable time, high level to high impedance RL = 100 Ω, 2.7 4 ns CL = 15 pF distributed, tPLZ Disable time, low level to high impedance 2.7 4 ns See Figure 3 tPZH Enable time, high impedance to high level 1 5 8 ns tPZL Enable time, high impedance to low level 1 5 8 ns fMAX Maximum operating frequency (4) 250 MHz LVCMOS Outputs (ROUT) tPLH Propagation delay low to high VID= 200 mV, 0.5 1.9 3.5 ns CL = 15 pF distributed, tPHL Propagation delay high to low 0.5 1.7 3.5 ns See Figure 4 tsk(p) Pulse skew (|tPHL - tPLH|) 0 0.2 0.4 ns tsk(o) Channel-to-channel skew (5) 0 0.05 0.5 ns tsk(pp) Part-to-part skew (6) 0 1 ns tr Rise time 0.3 0.5 1.4 ns tf Fall time 0.3 0.5 1.4 ns tPHZ Disable time, high level to high impedance CL = 15 pF distributed, 3 7.2 9 ns See Figure 5 tPLZ Disable time, low level to high impedance 2.5 4 8 ns tPZH Enable time, high impedance to high level 2.5 4.2 7 ns tPZL Enable time, high impedance to low level 2 3.3 7 ns fMAX Maximum operating frequency (7) 200 250 MHz (1) All typical values are at 25 °C and with a 3.3 V supply. (2) tsk(o) is the magnitude of the time difference between the tPLH or tPHL of all drivers of a single device with all of their inputs connected together. (3) tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits. (4) f(MAX) generator input conditions: tr = tf < 1 ns (0% to 100%), 50% duty cycle, 0 V to 3 V. Output Criteria: duty cycle = 45% to 55%, VOD > 250 mV, all channels switching. (5) tsk(lim) is the maximum delay time difference between drivers over temperature, VCC, and process. (6) tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate wf(MAX) generaith the same supply voltages, at the same temperature, and have identical packages and test circuits (7) f(MAX) generator input conditions: tr = tf < 1 ns (0% to 100%), 50% duty cycle, VID = 200 mV, VCM = 1.2 V. Output criteria: duty cycle = 45% to 55%, VOH > 2.7 V, VOL < 0.25 V, all channels switching. 5 |
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