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TLC59208F Datasheet(PDF) 6 Page - Texas Instruments |
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TLC59208F Datasheet(HTML) 6 Page - Texas Instruments |
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6 / 27 page  I 2C INTERFACE TIMING REQUIREMENTS TLC59208F SCLS715 – MARCH 2009 .................................................................................................................................................................................................. www.ti.com TA = –40°C to 85°C STANDARD-MODE FAST-MODE FAST-MODE PLUS I2C BUS I2C BUS I2C BUS UNIT MIN MAX MIN MAX MIN MAX I2C Interface fSCL SCL clock frequency 0 100 0 400 0 1000 kHz I2C bus free time between stop and tBUF 4.7 1.3 0.5 µs start tHD;STA Hold time (repeated) Start condition 4 0.6 0.26 µs Set-up time for a repeated Start tSU;STA 4.7 0.6 0.26 µs condition tSU;STO Set-up time for Stop condition 4 0.6 0.26 µs tHD;DAT Data hold time 0 0 0 ns tVD;ACK Data valid acknowledge time(1) 0.3 3.45 0.1 0.9 0.05 0.45 µs tVD;DAT Data valid time(2) 0.3 3.45 0.1 0.9 0.05 0.45 µs tSU;DAT Data set-up time 250 100 50 ns tLOW Low period of the SCL clock 4.7 1.3 0.5 µs tHIGH High period of the SCL clock 4 0.6 0.26 µs Fall time of both SDA and SCL tf 300 20+0.1Cb (5) 300 120 ns signals(3)(4) Rise time of both SDA and SCL tr 1000 20+0.1Cb (5) 300 120 ns signals Pulse width of spikes that must be tSP 50 50 50 ns suppressed by the input filter(6) Reset tW Reset pulse width 10 10 10 ns tREC Reset recovery time 0 0 0 ns tRESET Time to reset(7)(8) 400 400 400 ns (1) tVD;ACK = time for Acknowledgement signal from SCL low to SDA (out) low. (2) tVD;DAT = minimum time for SDA data out to be valid following SCL low. (3) A master device must internally provide a hold time of at least 300 ns for the SDA signal (refer to the VIL of the SCL signal) in order to bridge the undefined region of SCLs falling edge. (4) The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time (tf) for the SDA output stage is specified at 250 ns. This allows series protection resistors to be connected between the SDA and the SCL pins and the SDA/SCL bus lines without exceeding the maximum specified tf. (5) Cb = total capacitance of one bus line in pF. (6) Input filters on the SDA and SCL inputs suppress noise spikes less than 50 ns (7) Resetting the device while actively communicating on the bus may cause glitches or errant Stop conditions. (8) Upon reset, the full delay will be the sum of tRESET and the RC time constant of the SDA bus. 6 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TLC59208F |
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