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LM3S8938-EBZ20-A2 Datasheet(PDF) 10 Page - Texas Instruments

Part # LM3S8938-EBZ20-A2
Description  Stellaris짰 LM3S8938 Microcontroller
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

LM3S8938-EBZ20-A2 Datasheet(HTML) 10 Page - Texas Instruments

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Figure 15-1.
I2C Block Diagram ............................................................................................. 400
Figure 15-2.
I2C Bus Configuration ........................................................................................ 400
Figure 15-3.
START and STOP Conditions ............................................................................. 401
Figure 15-4.
Complete Data Transfer with a 7-Bit Address ....................................................... 401
Figure 15-5.
R/S Bit in First Byte ............................................................................................ 401
Figure 15-6.
Data Validity During Bit Transfer on the I2C Bus ................................................... 402
Figure 15-7.
Master Single SEND .......................................................................................... 405
Figure 15-8.
Master Single RECEIVE ..................................................................................... 406
Figure 15-9.
Master Burst SEND ........................................................................................... 407
Figure 15-10. Master Burst RECEIVE ...................................................................................... 408
Figure 15-11. Master Burst RECEIVE after Burst SEND ............................................................ 409
Figure 15-12. Master Burst SEND after Burst RECEIVE ............................................................ 410
Figure 15-13. Slave Command Sequence ................................................................................ 411
Figure 16-1.
CAN Controller Block Diagram ............................................................................ 436
Figure 16-2.
CAN Data/Remote Frame .................................................................................. 437
Figure 16-3.
Message Objects in a FIFO Buffer ...................................................................... 445
Figure 16-4.
CAN Bit Time .................................................................................................... 449
Figure 17-1.
Ethernet Controller ............................................................................................. 484
Figure 17-2.
Ethernet Controller Block Diagram ...................................................................... 484
Figure 17-3.
Ethernet Frame ................................................................................................. 485
Figure 17-4.
Interface to an Ethernet Jack .............................................................................. 491
Figure 18-1.
Analog Comparator Module Block Diagram ......................................................... 532
Figure 18-2.
Structure of Comparator Unit .............................................................................. 533
Figure 18-3.
Comparator Internal Reference Structure ............................................................ 533
Figure 19-1.
100-Pin LQFP Package Pin Diagram .................................................................. 543
Figure 19-2.
108-Ball BGA Package Pin Diagram (Top View) ................................................... 544
Figure 22-1.
Load Conditions ................................................................................................ 578
Figure 22-2.
JTAG Test Clock Input Timing ............................................................................. 580
Figure 22-3.
JTAG Test Access Port (TAP) Timing .................................................................. 581
Figure 22-4.
JTAG TRST Timing ............................................................................................ 581
Figure 22-5.
External Reset Timing (RST) .............................................................................. 582
Figure 22-6.
Power-On Reset Timing ..................................................................................... 582
Figure 22-7.
Brown-Out Reset Timing .................................................................................... 582
Figure 22-8.
Software Reset Timing ....................................................................................... 582
Figure 22-9.
Watchdog Reset Timing ..................................................................................... 583
Figure 22-10. Hibernation Module Timing ................................................................................. 584
Figure 22-11. ADC Input Equivalency Diagram ......................................................................... 585
Figure 22-12. SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing
Measurement .................................................................................................... 586
Figure 22-13. SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer ................. 586
Figure 22-14. SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ..................................... 587
Figure 22-15. I2C Timing ......................................................................................................... 588
Figure 22-16. External XTLP Oscillator Characteristics ............................................................. 590
Figure D-1.
100-Pin LQFP Package ...................................................................................... 617
Figure D-2.
108-Ball BGA Package ...................................................................................... 619
June 22, 2010
10
Texas Instruments-Production Data
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