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LM3S8530-IQN80-C1 Datasheet(PDF) 8 Page - Texas Instruments |
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LM3S8530-IQN80-C1 Datasheet(HTML) 8 Page - Texas Instruments |
8 / 526 page List of Figures Figure 1-1. Stellaris ® LM3S8530 Microcontroller High-Level Block Diagram ............................. 33 Figure 2-1. CPU Block Diagram ............................................................................................. 41 Figure 2-2. TPIU Block Diagram ............................................................................................ 42 Figure 5-1. JTAG Module Block Diagram ................................................................................ 52 Figure 5-2. Test Access Port State Machine ........................................................................... 55 Figure 5-3. IDCODE Register Format ..................................................................................... 61 Figure 5-4. BYPASS Register Format .................................................................................... 61 Figure 5-5. Boundary Scan Register Format ........................................................................... 62 Figure 6-1. Basic RST Configuration ...................................................................................... 64 Figure 6-2. External Circuitry to Extend Power-On Reset ........................................................ 65 Figure 6-3. Reset Circuit Controlled by Switch ........................................................................ 65 Figure 6-4. Power Architecture .............................................................................................. 67 Figure 6-5. Main Clock Tree .................................................................................................. 69 Figure 7-1. Flash Block Diagram .......................................................................................... 124 Figure 8-1. GPIO Port Block Diagram ................................................................................... 150 Figure 8-2. GPIODATA Write Example ................................................................................. 151 Figure 8-3. GPIODATA Read Example ................................................................................. 151 Figure 9-1. GPTM Module Block Diagram ............................................................................ 191 Figure 9-2. 16-Bit Input Edge Count Mode Example .............................................................. 195 Figure 9-3. 16-Bit Input Edge Time Mode Example ............................................................... 196 Figure 9-4. 16-Bit PWM Mode Example ................................................................................ 197 Figure 10-1. WDT Module Block Diagram .............................................................................. 227 Figure 11-1. UART Module Block Diagram ............................................................................. 251 Figure 11-2. UART Character Frame ..................................................................................... 252 Figure 11-3. IrDA Data Modulation ......................................................................................... 254 Figure 12-1. SSI Module Block Diagram ................................................................................. 291 Figure 12-2. TI Synchronous Serial Frame Format (Single Transfer) ........................................ 294 Figure 12-3. TI Synchronous Serial Frame Format (Continuous Transfer) ................................ 294 Figure 12-4. Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 .......................... 295 Figure 12-5. Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 .................. 295 Figure 12-6. Freescale SPI Frame Format with SPO=0 and SPH=1 ......................................... 296 Figure 12-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ............... 297 Figure 12-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 ........ 297 Figure 12-9. Freescale SPI Frame Format with SPO=1 and SPH=1 ......................................... 298 Figure 12-10. MICROWIRE Frame Format (Single Frame) ........................................................ 299 Figure 12-11. MICROWIRE Frame Format (Continuous Transfer) ............................................. 300 Figure 12-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ............ 300 Figure 13-1. I2C Block Diagram ............................................................................................. 329 Figure 13-2. I2C Bus Configuration ........................................................................................ 329 Figure 13-3. START and STOP Conditions ............................................................................. 330 Figure 13-4. Complete Data Transfer with a 7-Bit Address ....................................................... 330 Figure 13-5. R/S Bit in First Byte ............................................................................................ 330 Figure 13-6. Data Validity During Bit Transfer on the I2C Bus ................................................... 331 Figure 13-7. Master Single SEND .......................................................................................... 334 Figure 13-8. Master Single RECEIVE ..................................................................................... 335 June 22, 2010 8 Texas Instruments-Production Data Table of Contents |
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