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SN74AUP3G04DCUR Datasheet(PDF) 2 Page - Texas Instruments

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Part # SN74AUP3G04DCUR
Description  LOW-POWER TRIPLE INVERTER GATE
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

SN74AUP3G04DCUR Datasheet(HTML) 2 Page - Texas Instruments

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1
7
1A
1Y
3
5
2A
2Y
6
2
3A
3Y
SN74AUP3G04
SCES762B – DECEMBER 2009 – REVISED MARCH 2010
www.ti.com
The SN74AUP3G04 performs the Boolean function Y = A in positive logic.
NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the
package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION(1)
ORDERABLE
TOP-SIDE
TA
PACKAGE(2)
PART NUMBER
MARKING(3)
NanoStar™ – WCSP (DSBGA)
Reel of 3000
SN74AUP3G04YFPR
_ _ H C _
0.23-mm Large Bump – YFP (Pb-free)
uQFN – DQE
Reel of 5000
SN74AUP3G04DQER
T9
–40°C to 85°C
QFN – RSE
Reel of 5000
SN74AUP3G04RSER
T9
SSOP – DCU
Reel of 3000
SN74AUP3G04DCUR
H04_
(1)
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2)
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
(3)
DCU: The actual top-side marking has one additional character that designates the wafer fab/assembly site.
YFP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the wafer fab/assembly site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free).
FUNCTION TABLE
INPUT
OUTPUT
A
Y
H
L
L
H
LOGIC DIAGRAM (POSITIVE LOGIC)
(1)
Pin numbers shown are for the DCU and DQE packages.
2
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Copyright © 2009–2010, Texas Instruments Incorporated
Product Folder Link(s): SN74AUP3G04


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