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TLV320DAC3120 Datasheet(PDF) 57 Page - Texas Instruments |
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TLV320DAC3120 Datasheet(HTML) 57 Page - Texas Instruments |
57 / 110 page TLV320DAC3120 www.ti.com SLAS659 – NOVEMBER 2009 Page 0 / Register 27: Codec Interface Control READ/ RESET BIT DESCRIPTION WRITE VALUE D7–D6 R/W 00 00: Codec interface = I2S 01: Codec Interface = DSP 10: Codec interface = RJF 11: Codec interface = LJF D5–D4 R/W 00 00: Codec interface word length = 16 bits 01: Codec interface word length = 20 bits 10: Codec interface word length = 24 bits 11: Codec interface word length = 32 bits D3 R/W 0 0: BCLK is input. 1: BCLK is output. D2 R/W 0 0: WCLK is input. 1: WCLK is output. D1 R/W 0 Reserved D0 R/W 0 Reserved Page 0 / Register 28: Data-Slot Offset Programmability READ/ RESET BIT DESCRIPTION WRITE VALUE D7–D0 R/W 0000 0000 Offset (Measured With Respect to WCLK Rising Edge in DSP Mode) 0000 0000: Offset = 0 BCLKs 0000 0001: Offset = 1 BCLK 0000 0010: Offset = 2 BCLKs ... 1111 1110: Offset = 254 BCLKs 1111 1111: Offset = 255 BCLKs Page 0 / Register 29: Codec Interface Control 2 READ/ RESET BIT DESCRIPTION WRITE VALUE D7–D6 R/W 00 Reserved D5 R/W 0 Reserved D4 R/W 0 Reserved D3 R/W 0 0: BCLK is not inverted (valid for both primary and secondary BCLK). 1: BCLK is inverted (valid for both primary and secondary BCLK). D2 R/W 0 BCLK and WCLK Active Even With Codec Powered Down (Valid for Both Primary and Secondary BCLK) 0: Disabled 1: Enabled D1–D0 R/W 00 00: BDIV_CLKIN = DAC_CLK (DAC DSP clock - generated on-chip) 01: BDIV_CLKIN = DAC_MOD_CLK (generated on-chip) 10: Reserved 11: Reserved Page 0 / Register 30: BCLK N_VAL READ/ RESET BIT DESCRIPTION WRITE VALUE D7 R/W 0 0: BCLK N-divider is powered down. 1: BCLK N-divider is powered up. D6–D0 R/W 000 0001 000 0000: BCLK divider N = 128 000 0001: BCLK divider N = 1 000 0010: BCLK divider N = 2 ... 111 1110: BCLK divider N = 126 111 1111: BCLK divider N = 127 Copyright © 2009, Texas Instruments Incorporated REGISTER MAP 57 Submit Documentation Feedback Product Folder Link(s): TLV320DAC3120 |
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