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TMS320DM6467 Datasheet(PDF) 1 Page - Texas Instruments

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Part # TMS320DM6467
Description  Digital Media System-on-Chip
Download  357 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TMS320DM6467 Datasheet(HTML) 1 Page - Texas Instruments

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1
Digital Media System-on-Chip (DMSoC)
1.1 Features
TMS320DM6467
Digital Media System-on-Chip
www.ti.com
SPRS403F – DECEMBER 2007 – REVISED OCTOBER 2009
(Flexible RAM/Cache Allocation)
• High-Performance Digital Media SoC
• ARM926EJ-S Core
594-, 729-MHz C64x+™ Clock Rate
Support for 32-Bit and 16-Bit (Thumb®
297-, 364.5-MHz ARM926EJ-S™ Clock Rate
Mode) Instruction Sets
Eight 32-Bit C64x+ Instructions/Cycle
DSP Instruction Extensions and Single
4752, 5832 C64x+ MIPS
Cycle MAC
Fully Software-Compatible With C64x /
ARM® Jazelle® Technology
ARM9™
EmbeddedICE-RT™ Logic for Real-Time
Supports SmartReflex™ Class 0 [-594 only]
Debug
• 1.05-V and 1.2-V Adaptive Core Voltage
• ARM9 Memory Architecture
Extended Temp Available [-594 only]
16K-Byte Instruction Cache
Industrial Temp Available [-729 only]
8K-Byte Data Cache
• Advanced Very-Long-Instruction-Word (VLIW)
32K-Byte RAM
TMS320C64x+™ DSP Core
8K-Byte ROM
Eight Highly Independent Functional Units
• Embedded Trace Buffer™ (ETB11™) With 4KB
• Six ALUs (32-/40-Bit), Each Supports
Memory for ARM9 Debug
Single 32-Bit, Dual 16-Bit, or Quad 8-Bit
Arithmetic per Clock Cycle
• Endianness: Little Endian for ARM and DSP
• Two Multipliers Support Four 16 x 16-Bit
• Dual Programmable High-Definition Video
Multiplies (32-Bit Results) per Clock
Image Co-Processor (HDVICP) Engines
Cycle or Eight 8 x 8-Bit Multiplies (16-Bit
Supports a Range of Encode, Decode, and
Results) per Clock Cycle
Transcode Operations
Load-Store Architecture With Non-Aligned
• H.264, MPEG2, VC1, MPEG4 SP/ASP
Support
• 99-/108-MHz Video Port Interface (VPIF)
64 32-Bit General-Purpose Registers
Two 8-Bit SD (BT.656), Single 16-Bit HD
Instruction Packing Reduces Code Size
(BT.1120), or Single Raw (8-/10-/12-Bit)
All Instructions Conditional
Video Capture Channels
Additional C64x+™ Enhancements
Two 8-Bit SD (BT.656) or Single 16-Bit HD
• Protected Mode Operation
(BT.1120) Video Display Channels
• Exceptions Support for Error Detection
• Video Data Conversion Engine (VDCE)
and Program Redirection
Horizontal and Vertical Downscaling
• Hardware Support for Modulo Loop
Chroma Conversion (4:2:2
↔4:2:0)
Operation
• Two Transport Stream Interface (TSIF)
• C64x+ Instruction Set Features
Modules
Byte-Addressable (8-/16-/32-/64-Bit Data)
(One Parallel/Serial and One Serial Only)
8-Bit Overflow Protection
TSIF for MPEG Transport Stream
Bit-Field Extract, Set, Clear
Simultaneous Synchronous or
Normalization, Saturation, Bit-Counting
Asynchronous Input/Output Streams
Compact 16-Bit Instructions
Absolute Time Stamp Detection
Additional Instructions to Support Complex
PID Filter With 7 PID Filter Tables
Multiplies
Corresponding Clock Reference Generator
• C64x+ L1/L2 Memory Architecture
(CRGEN) Modules for System Time-Clock
32K-Byte L1P Program RAM/Cache (Direct
Recovery
Mapped)
32K-Byte L1D Data RAM/Cache (2-Way
Set-Associative)
128K-Byte L2 Unified Mapped RAM/Cache
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this document.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 2007–2009, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.


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