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SN74AUP1G97DBVT Datasheet(PDF) 2 Page - Texas Instruments

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Part # SN74AUP1G97DBVT
Description  LOW-POWER CONFIGURABLE MULTIPLE-FUNCTION GATE
Download  26 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

SN74AUP1G97DBVT Datasheet(HTML) 2 Page - Texas Instruments

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Time − ns
Output
Input
Switching Characteristics
at 25 MHz
AUP1G08 data at CL = 15 pF
AUP
LVC
AUP
AUP
LVC
Static-Power Consumption
(
µA)
Dynamic-Power Consumption
(pF)
Single, dual, and triple gates
3.3-V
Logic
3.3-V
Logic
0%
20%
40%
60%
80%
100%
0%
20%
40%
60%
80%
100%
SN74AUP1G97
SCES505J – NOVEMBER 2003 – REVISED MAY 2010
www.ti.com
Figure 1. AUP – The Lowest-Power Family
Figure 2. Excellent Signal Integrity
The SN74AUP1G97 features configurable multiple functions. The output state is determined by eight patterns of
3-bit input. The user can choose the logic functions MUX, AND, OR, NAND, NOR, inverter, and noninverter. All
inputs can be connected to VCC or GND.
The device functions as an independent gate with Schmitt-trigger inputs, which allows for slow input transition
and better switching-noise immunity at the input.
NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the
package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION(1)
TA
PACKAGE(2)
ORDERABLE PART NUMBER
TOP-SIDE MARKING(3)
NanoStar™ – WCSP (DSBGA)
Reel of 3000
SN74AUP1G97YFPR
_ _ _HP_
0.23-mm Large Bump – YFP (Pb-free)
NanoStar™ – WCSP (DSBGA)
Reel of 3000
SN74AUP1G97YZPR
_ _ _HP_
0.23-mm Large Bump – YZP (Pb-free)
QFN – DRY
Reel of 5000
SN74AUP1G97DRYR
HP
–40°C to 85°C
uQFN – DSF
Reel of 5000
SN74AUP1G97DSFR
HP
SOT (SOT-23) – DBV
Reel of 3000
SN74AUP1G97DBVR
H97_
SOT (SC-70) – DCK
Reel of 3000
SN74AUP1G97DCKR
HP_
SOT (SOT-553) – DRL
Reel of 4000
SN74AUP1G97DRLR
(1)
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2)
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
(3)
DBV/DCK/DRL: The actual top-side marking has one additional character that designates the wafer fab/assembly site.
YFP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the wafer fab/assembly site. Pin 1 identifier indicates solder-bump composition (1 = SnPb,
● = Pb-free).
FUNCTION TABLE
INPUTS
OUTPUT
Y
C
B
A
L
L
L
L
L
L
H
L
L
H
L
H
L
H
H
H
H
L
L
L
H
L
H
H
H
H
L
L
H
H
H
H
2
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Copyright © 2003–2010, Texas Instruments Incorporated
Product Folder Link(s): SN74AUP1G97


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