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SN74AUP1G06DCKT Datasheet(PDF) 2 Page - Texas Instruments |
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SN74AUP1G06DCKT Datasheet(HTML) 2 Page - Texas Instruments |
2 / 21 page AUP LVC AUP AUP LVC Static-PowerConsumption ( A) m Dynamic-PowerConsumption (pF) Single,dual,andtriplegates † 3.3-V Logic † 0% 20% 40% 60% 80% 100% 0% 20% 40% 60% 80% 100% 3.3-V Logic † -0.5 0 0.5 1 1.5 2 2.5 3 3.5 0 5 10 15 20 25 30 35 40 45 Time-ns † AUP1G08dataatC =15pF L Output Input SwitchingCharacteristics at25MHz † A Y 2 4 SN74AUP1G06 SCES590D – JULY 2004 – REVISED MAY 2010 www.ti.com DESCRIPTION/ORDERING INFORMATION The AUP family is TI's premier solution to the industry's low-power needs in battery-powered portable applications. This family ensures a very low static and dynamic power consumption across the entire VCC range of 0.8 V to 3.6 V, resulting in an increased battery life. This product also maintains excellent signal integrity (see Figure 1 and Figure 2). Figure 1. AUP – The Lowest-Power Family Figure 2. Excellent Signal Integrity The output of this single inverter buffer/driver is open drain, and can be connected to other open-drain outputs to implement active-low wired-OR or active-high wired-AND functions. NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the package. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. ORDERING INFORMATION(1) TA PACKAGE(2) ORDERABLE PART NUMBER TOP-SIDE MARKING(3) NanoStar™ – WCSP (DSBGA) Reel of 3000 SN74AUP1G06YFPR _ _ _HT_ 0.23-mm Large Bump – YFP QFN – DRY Reel of 5000 SN74AUP1G06DRYR HT uQFN – DSF Reel of 5000 SN74AUP1G06DSFR HT –40°C to 85°C Reel of 3000 SN74AUP1G06DBVR SOT (SOT-23) – DBV H06_ Reel of 250 SN74AUP1G06DBVT Reel of 3000 SN74AUP1G06DCKR SOT (SC-70) – DCK HT_ Reel of 250 SN74AUP1G06DCKT (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. (2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. (3) DBV/DCK: The actual top-side marking has one additional character that designates the wafer fab/assembly site. YFP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following character to designate the wafer fab/assembly site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free). FUNCTION TABLE INPUT OUTPUT A Y H L L Z LOGIC DIAGRAM (POSITIVE LOGIC) 2 Submit Documentation Feedback Copyright © 2004–2010, Texas Instruments Incorporated Product Folder Link(s): SN74AUP1G06 |
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