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SN74LV164ADRE4 Datasheet(PDF) 2 Page - Texas Instruments |
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SN74LV164ADRE4 Datasheet(HTML) 2 Page - Texas Instruments |
2 / 21 page SN54LV164A, SN74LV164A 8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS SCLS403H − APRIL 1998 − REVISED APRIL 2005 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 description/ordering information (continued) These devices feature AND-gated serial (A and B) inputs and an asynchronous clear (CLR) input. The gated serial inputs permit complete control over incoming data, as a low at either input inhibits entry of the new data and resets the first flip-flop to the low level at the next clock pulse. A high-level input enables the other input, which then determines the state of the first flip-flop. Data at the serial inputs can be changed while the clock is high or low, provided the minimum setup time requirements are met. Clocking occurs on the low-to-high-level transition of the clock (CLK) input. FUNCTION TABLE INPUTS OUTPUTS CLR CLK A B QA QB ...QH L X X X L L L H LX X QA0 QB0 QH0 H ↑ HH H QAn QGn H ↑ LX L QAn QGn H ↑ X L L QAn QGn QA0, QB0, QH0 = the level of QA, QB, or QH, respectively, before the indicated steady-state input conditions were established. QAn, QGn = the level of QA or QG before the most recent ↑ transition of the clock: indicates a 1-bit shift. logic diagram (positive logic) C1 1D R C1 1D R QA QB C1 1D R C1 1D R QC QD C1 1D R C1 1D R QE QF C1 1D R C1 1D R QG QH 345 6 10 11 12 13 8 1 2 9 CLK A B CLR Pin numbers shown are for the D, DB, DGV, J, NS, PW, RGY, and W packages. |
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