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TPS23754 Datasheet(PDF) 11 Page - Texas Instruments |
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TPS23754 Datasheet(HTML) 11 Page - Texas Instruments |
11 / 41 page TJ − Junction Temperature − °C 910 920 930 940 950 960 970 −40 −20 0 20 40 60 80 100 120 G002 Pulsed Current Measurement (VVDD − VVSS) − PoE Voltage − V 0 1 2 3 4 5 6 7 8 0 2 4 6 8 10 G001 −40 °C 25 °C 125 °C TPS23754 TPS23754-1 TPS23756 www.ti.com SLVS885D – OCTOBER 2008 – REVISED DECEMBER 2009 A minimum 0.47 μF capacitor, located adjacent to the VC pin, should be connected from VC to COM to bypass the gate driver. A larger total capacitance is required for startup to provide control power between the time the converter starts switching and the availability of the converter auxiliary output voltage. VDD VDD is the positive input power rail that is derived from the PoE source (PSE). VDD should be bypassed to VSS with a 0.1 μF capacitor as required by the IEEE standard. A transient suppressor diode (TVS), a special type of Zener diode, such as SMAJ58A should be connected from VDD to VSS to protect against over-voltage transients. VDD1 VDD1 is the dc/dc converter startup supply. Connect to VDD for many applications. VDD1 may be isolated by a diode from VDD to support PoE priority operation. VSS VSS is the PoE input-power return side. It is the reference for the PoE interface circuits, and has a current-limited hotswap switch that connects it to RTN. VSS is clamped to a diode drop above RTN by the hotswap switch. A local VSS reference plane should be used to connect the input bypass capacitor, TVS, RCLS, and the PowerPad. This plane becomes the main heatsink for the TPS23754. VSS is internally connected to the PowerPAD. PowerPAD The Powerpad is internally connected to VSS. It should be tied to a large VSS copper area on the PCB to provide a low resistance thermal path to the circuit board. It is recommended that a clearance of 0.025” be maintained between VSS, RTN, and various control signals to high-voltage signals such as VDD and VDD1. TYPICAL CHARACTERISTICS DETECTION BIAS CURRENT PoE CURRENT LIMIT vs vs VOLTAGE TEMPERATURE Figure 3. Figure 4. Copyright © 2008–2009, Texas Instruments Incorporated Submit Documentation Feedback 11 |
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