P3PS550AH

http://onsemi.com

4

Table 6. AC ELECTRICAL CHARACTERISTICS

Symbol

Parameter

Min

Typ

Max

Unit

CLKIN

Input Clock frequency

18

24

36

MHz

ModOUT

Output Clock frequency

18

24

36

MHz

Output rise time

(Measured between 20% to 80%)

Unloaded Output

0.4

0.8

ns

1.4

2.2

Output fall time

(Measured between 80% to 20%)

Unloaded Output

0.3

0.6

ns

1.1

1.9

Jitter (cycle to cycle) Unloaded Output

$175

$250

ps

Output duty cycle

45

50

55

%

PLL lock Time

(Stable power supply, valid clock presented on CLKIN pin,

PD# toggled from Low to High)

3

ms

Frequency Deviation Variation across PVT

$2.5

$5

%

1. Parameter is guaranteed by design and characterization. Not 100% tested in production

Figure 2. Typical Application Schematic

NOTE: Refer Pin Description table for Functionality details.

CLKIN

VSS

VDD

2.2mF

C2

ModOUT

ModOUT Clock

P3PS550AH

SR2, SR1, SR0

Frequency Deviation

Selection Control

VDD

0 W

0 W

0.1mF

M Clock

R

Rs

0 W

0 W

VDD

PD#

C1

SR2/SR1/SR0

Power Down

Control

VDDIN

1

2,6,7

5

3

8

4

PCB Layout Recommendation

For optimum device performance, following guidelines are recommended.

mounted on the component side of the board as close to the VDD pin as possible. No vias should be used between the

decoupling capacitor and VDD pin. The PCB trace to VDD pin and the ground via should be kept as short as possible.

All the VDD pins should have decoupling capacitors.

A typical layout is shown in the figure