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 2006 Semtech Corp.

www.semtech.com

PRELIMINARY

PROTECTION PRODUCTS

EClamp2410P

Applications Information

Device Connection

The EClamp2410P is a microSD/T-Flash interface device

designed for use in cell phones and other portable

electronic devices. The EClamp2410P is comprised of

series and pull up resistors required on the microSD

interface. Each line also includes TVS diodes for ESD

protection. The device may be configured for SD or SPI

mode operation. In SD mode for example, the 15k Ohm

pull up resistors (Rup 1 and Rup 3) are connected to

VDD. In SPI mode pin 4 is not connected (Rup 1) since

these are reserved lines. The 50k Ohm pull up resistor

is used for card detection or SPI mode selection during

power up and is disconnected by the user during regular

data transfer.

The EClamp2410P is in a 16-pin SLP package. Electrical

connection is made to the 16 pins located at the bottom

of the device. The device has a flow through design for

easy layout. Pin connections are noted in Figure 1. A

center tab serves as the ground connection. Recom-

mendations for the ground connection are given below.

Ground Connection Recommendation

Parasitic inductance present in the board layout will

affect the filtering and ESD performance of the device.

Ground loop inductance can be reduced by using mul-

tiple vias to make the connection to the ground plane.

Figure 2 shows the recommended device layout. The

ground pad vias have a diameter of 0.008 inches (0.20

mm) while the two external vias have a diameter of

0.010 inches (0.250mm). The internal vias are spaced

approximately evenly from the center of the pad. The

designer may choose to use more vias with a smaller di-

ameter (such as 0.005 inches or 0.125mm) since chang-

ing the diameter of the via will result in little change in

inductance.

Layout Guidelines for Optimum ESD Protection

Good circuit board layout is critical not only for signal

integrity, but also for effective suppression of ESD

induced transients. For optimum ESD protection, the

following guidelines are recommended:

Place the device as close to the connector as

possible. This practice restricts ESD coupling into

adjacent traces and reduces parasitic inductance.

The ESD transient return path to ground should be

kept as short as possible. Whenever possible, use

multiple micro vias connected directly from the

device ground pad to the ground plane.

Avoid running critical signals near board edges.

Figure 1 - Pin Identification and Configuration

(Top Side View)

DAT1 In

DAT0 In

CL K In

R up1

1

Vd d

CMD In

DAT3 In

DAT2 In

DAT2 O u t

DAT3 O u t

CMD O u t

R up2

R up3

CL K O u t

DAT1 O u t

DAT0 O u t

16

Figure 2 - Recommended Layout using Ground Vias