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BR24L04FV-W Datasheet(PDF) 6 Page - Rohm |
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BR24L04FV-W Datasheet(HTML) 6 Page - Rohm |
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6 / 25 page  BR24L04-W / BR24L04F-W / BR24L04FJ-W Memory ICs BR24L04FV-W / BR24L04FVM-W 6/25 Synchronous data timing tBUF tPD tHIGH tHD : STA tLOW tF tR SCL START BIT STOP BIT SCL SDA tDH tSU : DAT tHD : DAT tSU : STO tHD : STA tSU : STA SDA (OUT) SDA (IN) Fig.4 SYNCHRONOUS DATA TIMING •SDA data is latched into the chip at the rising edge of SCL clock. •Output data toggles at the falling edge of SCL clock. Write cycle timing ACK D0 tWR SDA SCL START CONDITION STOP CONDITION WRITE DATA (n) Fig.5 WRITE CYCLE TIMING |
Similar Part No. - BR24L04FV-W |
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