6

Memory ICs

BR93LL46F / BR93LL46FV

(4) Write

A0

A1

10

D15 D14

D0

D1

READY

BUSY

STATUS

1A5

A4

12

4

9

10

25

CS

SK

DI

DO

High-Z

Fig. 4 Write cycle timing (WRITE)

10

0

00

CS

SK

DI

DO

High-Z

Fig. 5 Write disable cycle timing (WDS)

This command writes the 16-bit data (D15 to D0) to the

specified address (A5 to A0). The actual writing begins

when CS falls following the fall of the SK cloc (the 25th

clock pulse after the start bit) when D0 is read.

If STATUS is not detected (CS is fixed at LOW, or if

commands will be received as long as a LOW state

(BUSY) is output from DO, so command input should

be avoided.

∗ STATUS

write command, if CS is set to HIGH, the write execute

= BUSY (LOW) and the command wait status READY

(HIGH) are output.

If in the command wait status (STATUS = READY), the

Thus, if data is input via SK and DI with CS = HIGH in

formed. To avoid this, make sure that DI = LOW when

CS = HIGH. (Caution is especially important when

common input ports are used.) This applies to all of the

write commands.

(5) Write disable

When the power supply is turned on, if the write enable

command is issued, the write enable state is entered. If

the write disable command is then issued, the IC

enters the write disable status. When in this status, all

write commands are ignored, but read commands may

be executed.

In the write enable status, writing begins even if a write

command is entered accidentally. To prevent errors of

this type, we recommend executing a write disable

command after writing has been completed.