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R5421N112C-TR Datasheet(PDF) 9 Page - RICOH electronics devices division |
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R5421N112C-TR Datasheet(HTML) 9 Page - RICOH electronics devices division |
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9 / 19 page  Rev.1.11 - 9 - s OPERATION q VD1 / Over-Charge Detector in the 'C' version The VD1 monitors VDD pin voltage. When the VDD voltage crosses over-charge detector threshold VDET1 from a low value to a value higher than the VDET1, the VD1 can sense a over-charging and an external charge control Nch-MOS-FET turns to “OFF” with COUT pin being at “Low” level. There can be two cases to reset the VD1 making the COUT pin level to “High” again after detecting over-charge. Resetting the VD1 can make charging system allowable to resumption of charging process. The first case is in such conditions that a time when the VDD voltage is coming down to a level lower than “VREL1”. While in the second case, connecting a kind of loading to VDD after disconnecting a charger from the battery pack can make the VD1 resetting when the VDD level is in between “VDET1” and “VREL1”. After detecting over-charge with the VDD voltage of higher than VDET1, connecting system load to the battery pack makes load current allowable through parasitic diode of external charge control FET. The COUT level would be High when the VDD level is coming down to a level below the VDET1 by continuous drawing of load current. An output delay time for over-charge detection can be set by external capacitor C3 connecting between the VSS pin and Ct pin. The external capacitor can make a delay time from a moment detecting over-charge to a time output a signal which enables charge control FET turn to “OFF”. When the VDD level is going up to a higher level than VDET1 if the VDD voltage would be back to a level lower than the VDET1 within a time period of the output delay time, VD1 would not output a signal for turning “OFF” of charge control FET. The output delay time can be calculated as below: tVDET1[sec] = (C3[F] × (VDD[V]-0.7) / (0.48 × 10-6) Note:Topt=25°C VDD value should be after over-charge detection. A level shifter incorporated in a buffer driver for the COUT pin makes the “Low” level of COUT pin to the V - pin voltage and the “High” level of COUT pin is set to VDD voltage with CMOS buffer. q VD2 / Over-Discharge Detector The VD2 is monitoring a VDD pin voltage. When the VDD voltage crosses the over-discharge detector threshold VDET2 from a high value to a value lower than the VDET2, the VD2 can sense an over-discharging and the external discharge control Nch MOS FET turns to “OFF” with the DOUT pin being at “Low” level. To reset the VD2 with the DOUT pin level being “H” again after detecting over-discharge it is necessary to connect a charger to the battery pack for R5421NxxxC. When the VDD voltage stays under over- discharge detector threshold VDET2 charge current can flow through parasitic diode of external discharge control MOS FET, then after the VDD voltage comes up to a value larger than VDET2, DOUT becomes "H" and discharging process would be able to advance through ON state MOS FET for discharge control. Connecting a charger to the battery pack makes the DOUT level being “H” instantaneously when the VDD voltage is higher than VDET2. Besides, for R5421NxxxF, when a cell voltage reaches equal or more than over-discharge released voltage, or VREL2, over- discharge condition can be also released When a cell voltage equals to zero, connecting charger to the battery pack makes the system allowable to charge with higher charge voltage than Vst, 1.2V Max. An output delay time for the over-discharge detection is fixed internally, tVDET2=10ms typ. at VDD=2.4V. When the VDD level is going down to a lower level than VDET2 if the VDD voltage would be back to a level higher than the VDET2 within a time period of the output delay time, VD2 would not output a signal for turning “OFF” of discharge control FET. After detection of an over-discharge by VD2, supply current would be reduced to typically 0.3µA(for R5421NxxxC) or 1.0 µA(for R5421NxxxF) at VDD=2.0V and into standby, only the charger detector is operating. The output type of DOUT pin is CMOS having “H” level of VDD and “L” level of VSS. |
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