K6R1008C1C-C/C-L, K6R1008C1C-I/C-P

CMOS SRAM

PRELIMINARY

Revision 3.0

- 2 -

September 2001

PRELIMINARY

128K x 8 Bit High-Speed CMOS Static RAM(5.0V Operating)

GENERAL DESCRIPTION

FEATURES

• Fast Access Time 10,12,15ns(Max.)

• Low Power Dissipation

Standby (TTL)

: 30mA(Max.)

(CMOS) : 5mA(Max.)

0.5mA(Max.) L-ver. only

Operating K6R1008C1C-10 : 80mA(Max.)

K6R1008C1C-12 : 75mA(Max.)

K6R1008C1C-15 : 73mA(Max.)

• Single 5.0V

±10% Power Supply

• TTL Compatible Inputs and Outputs

• I/O Compatible with 3.3V Device

• Fully Static Operation

- No Clock or Refresh required

• Three State Outputs

• 2V Minimum Data Retention: L-ver. only

• Center Power/Ground Pin Configuration

• Standard Pin Configuration

K6R1008C1C-J : 32-SOJ-400

K6R1008C1C-T : 32-TSOP2-400CF

K6R1008C1C-C10/C12/C15

Commercial Temp.

K6R1008C1C-I10/I12/I15

Industrial Temp.

ORDERING INFORMATION

Clk Gen.

CS

WE

OE

FUNCTIONAL BLOCK DIAGRAM

Data

Cont.

Column Select

CLK

Gen.

Pre-Charge Circuit

Memory Array

512 Rows

256x8 Columns

I/O Circuit

PIN FUNCTION

Pin Name

Pin Function

Address Inputs

WE

Write Enable

CS

Chip Select

OE

Output Enable

Data Inputs/Outputs

Power(+5.0V)

Ground

N.C

No Connection

The K6R1008C1C is a 1,048,576-bit high-speed Static Ran-

dom Access Memory organized as 131,072 words by 8 bits.

The K6R1008C1C uses 8 common input and output lines and

has an output enable pin which operates faster than address

access time at read cycle. The device is fabricated using SAM-

SUNG

′s advanced CMOS process and designed for high-

speed circuit technology. It is particularly well suited for use in

high-density

high-speed

system

applications.

The

K6R1008C1C is packaged in a 400mil 32-pin plastic SOJ or

TSOP2 forward.

SOJ/

TSOP2

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

OE

Vss

Vcc

CS

Vcc

Vss

WE