KM48C2000B, KM48C2100B

CMOS DRAM

KM48V2000B, KM48V2100B

NOTES

An initial pause of 200us is required after power-up followed by any 8 ROR or CBR cycles before proper device operation is

achieved.

Measured with a load equivalent to 2 TTL(5V)/1TTL(3.3V) loads and 100pF.

Operation within the

If

characteristics only. If

the duration of the cycle. If

read-modify-write cycle and the data output will contain the data read from the selected address. If neither of the above condi-

tions is satisfied, the condition of the data out is indeterminate.

Either

These parameters are referenced to the CAS falling edge in ealy write cycles and to the W falling edge in OE controlled write

cycle and read-modify-write cycles.

Operation within the

If

These specifications are applied in the test mode.

In test mode read cycle, the values of

ters should be specified in test mode cycles by adding 5ns to the specified value in this data sheet.

For all of the refresh modes except for distributed CAS -before- RAS refresh, 4096(4K Ref.)/2048(2K Ref.) cycles of burst

refresh must be executed within 16ms before and after self-refresh in order to meet refresh specification.

7.

6.

5.

9.

8.

3.

2.

1.

4.

10.

11.

12.