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KM681000BLTE-10 Datasheet(PDF) 5 Page - Samsung semiconductor |
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KM681000BLTE-10 Datasheet(HTML) 5 Page - Samsung semiconductor |
5 / 11 page PRELIMINARY Revision 0.3 KM681000B Family CMOS SRAM April 1996 TEST CONDITIONS(2. Temperature and Vcc Conditions) Product Family Temperature Power Supply(Vcc) Speed Bin Comments KM681000BL/L-L 0~70¡É 5.0V¡¾10% 55/70ns Commercial KM681000BLE/LE-L -25~85¡É 5.0V¡¾10% 70/100ns Extended KM681000BLI/LI-L -40~85¡É 5.0V¡¾10% 70/100ns Industrial PARAMETER LIST FOR EACH SPEED BIN Parameter List Symbol Speed Bins Units 55ns 70ns 100ns Min Max Min Max Min Max Read Read cycle time tRC 55 - 70 - 100 - ns Address access time tAA - 55 - 70 - 100 ns Chip select to output tCO1,tCO2 - 55 - 70 - 100 ns Output enable to valid output tOE - 25 - 35 - 50 ns Chip select to low-Z output tLZ1,tLZ2 10 - 10 - 10 - ns Output enable to low-Z output tOLZ 5 - 5 - 5 - ns Chip disable to high-Z output tHZ1,tHZ2 0 20 0 25 0 30 ns Output disable to high-Z output tOHZ 0 20 0 25 0 30 ns Output hold from address change tOH 10 - 10 - 10 - ns Write Write cycle time tWC 55 - 70 - 100 - ns Chip select to end of write tCW 45 - 60 - 80 - ns Address set-up time tAS 0 - 0 - 0 - ns Address valid to end of write tAW 45 - 60 - 80 - ns Write pulse width tWP 40 - 50 - 60 - ns Write recovery time tWR 0 - 0 - 0 - ns Write to output high-Z tWHZ 0 20 0 25 0 30 ns Data to write time overlap tDW 25 - 30 - 40 - ns Data hold from write time tDH 0 - 0 - 0 - ns End write to output low-Z tOW 5 - 5 - 5 - ns |
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