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TLV70015DSET Datasheet(PDF) 11 Page - Texas Instruments

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Part # TLV70015DSET
Description  200-mA, Low-IQ, Low-Dropout Regulator for Portable Devices
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TLV70015DSET Datasheet(HTML) 11 Page - Texas Instruments

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t
=
(120
R )
(120+R )
L
L
·
·
C
OUT
TLV700xx
TLV701xx
www.ti.com
SLVSA00A – SEPTEMBER 2009 – REVISED APRIL 2010
APPLICATION INFORMATION
The TLV700xx/TLV701xx belong to a new family of
next-generation value LDO regulators. These devices
Board Layout Recommendations to Improve
consume low quiescent current and deliver excellent
PSRR and Noise Performance
line
and
load
transient
performance.
These
Input and output capacitors should be placed as
characteristics, combined with low noise, very good
close to the device pins as possible. To improve ac
PSRR with little (VIN – VOUT) headroom, make this
performance such as PSRR, output noise, and
family of devices ideal for RF portable applications.
transient response, it is recommended that the board
This family of regulators offers sub-bandgap output
be designed with separate ground planes for VIN and
voltages down to 0.7 V, current limit, and thermal
VOUT, with the ground plane connected only at the
protection, and is specified from –40°C to +125°C.
GND pin of the device. In addition, the ground
connection
for
the
output
capacitor
should
be
Input and Output Capacitor Requirements
connected directly to the GND pin of the device. High
1.0-mF X5R- and X7R-type ceramic capacitors are
ESR capacitors may degrade PSRR performance.
recommended
because
these
capacitors
have
minimal variation in value and equivalent series
Internal Current Limit
resistance (ESR) over temperature.
The TLV700xx/TLV701xx internal current limit helps
However, the TLV700xx/TLV701xx are designed to
to protect the regulator during fault conditions. During
be stable with an effective capacitance of 0.1 mF or
current limit, the output sources a fixed amount of
larger at the output. Thus, the device is stable with
current that is largely independent of the output
capacitors of other dielectric types as well, as long as
voltage. In such a case, the output voltage is not
the
effective
capacitance
under
operating
bias
regulated, and is VOUT = ILIMIT × RLOAD. The PMOS
voltage and temperature is greater than 0.1 mF. This
pass transistor dissipates (VIN – VOUT) × ILIMIT until
effective capacitance refers to the capacitance that
thermal shutdown is triggered and the device turns
the LDO sees under operating bias voltage and
off. As the device cools down, it is turned on by the
temperature conditions; that is, the capacitance after
internal thermal shutdown circuit. If the fault condition
taking both bias voltage and temperature derating
continues, the device cycles between current limit
into consideration. In addition to allowing the use of
and thermal shutdown. See the Thermal Information
cheaper dielectrics, this capability of being stable with
section for more details.
0.1-mF effective capacitance also enables the use of
The PMOS pass element in the TLV700xx/TLV701xx
smaller footprint capacitors that have higher derating
has a built-in body diode that conducts current when
in size- and space-constrained applications.
the voltage at OUT exceeds the voltage at IN. This
Note that using a 0.1-mF rated capacitor at the output
current is not limited, so if extended reverse voltage
of the LDO does not ensure stability because the
operation is anticipated, external limiting to 5% of the
effective capacitance under the specified operating
rated output current is recommended.
conditions would be less than 0.1 mF. Maximum ESR
should be less than 200 m
Ω.
Shutdown
Although an input capacitor is not required for
The enable pin (EN) is active high. The device is
stability, it is good analog design practice to connect
enabled when voltage at EN pin goes above 0.9V.
a 0.1-mF to 1.0-mF, low ESR capacitor across the IN
This relatively lower value of voltage required to turn
pin and GND in of the regulator. This capacitor
the LDO on can be exploited to power the LDO with a
counteracts reactive input sources and improves
GPIO of recent processors whose GPIO Logic 1
transient
response,
noise
rejection,
and
ripple
voltage level is lower than traditional microcontrollers.
rejection. A higher-value capacitor may be necessary
The device is turned OFF when the EN pin is held at
if large, fast rise-time load transients are anticipated,
less than 0.4V. When shutdown capability is not
or if the device is not located close to the power
required, EN can be connected to the IN pin.
source. If source impedance is more than 2
Ω, a
The TLV701 has an internal active pull-down circuitry
0.1-mF input capacitor may be necessary to ensure
that discharges the output with a time constant of:
stability.
with:
RL = Load resistance
COUT = Output capacitor
(1)
Copyright © 2009–2010, Texas Instruments Incorporated
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