LIM

PROG

LIM

P

V

10

I

=

´

J(MAX )

S(MAX )

LIM

JC(MAX )

T

T

P

R

Q

-

<

TPS2492

TPS2493

SLUSA65A – JULY 2010 – REVISED AUGUST 2010

www.ti.com

VREF: Provides a 4.0-V reference voltage for use in conjunction with R4/R5 of the Typical Application Circuit to

set the voltage on the PROG pin. The reference voltage is available once the internal POR and UVLO thresholds

have been met. It is not designed as a supply voltage for other circuitry, therefore ensure that no more than 1 mA

is drawn. Bypass capacitance is not required, but if a special application requires one, less than 1000 pF can be

placed on this pin. This limit maintains VREG regulator stability.

PROG: The voltage applied to this pin (0.4 V minimum) programs the power limit used by the constant power

engine. Normally, a resistor divider R4/R5 is connected from VREF to PROG to set the power limit according to

the following equation:

(2)

by the desired thermal stress on M1:

(3)

A capacitor may be tied from PROG to ground to alter the natural constant power inrush current shape. If

properly designed, the effect is to cause the leading step of current in Figure 13 to look like a ramp. It is not

recommended that this mechanism be used to achieve a long and low ramp inrush current because the power

are not satisfied or the TPS2492 is latched off. This feature serves to discharge any capacitance connected to

the pin. Do not apply voltages greater than 4 V to PROG. If the constant power limit is not used, PROG should

be tied to VREF through a 47-k

Ω resistor.

restart interval for the TPS2493. The timer charges at 27 µA whenever the TPS2492/3 is in power limit or current

limit and discharges at 2.7 µA otherwise. The charge-to-discharge current ratio is constant with temperature even

The TPS2493 holds GATE at ground when the timer expires before it attempts to restart (re-enable GATE) after

a timing sequence consisting of discharging TIMER down to 1 V followed by 15 more charge and discharge

accommodate a restart.

The TPS2492 can be reset by either cycling the UVEN pin or the UVLO (e.g. power cycling). TIMER discharges

when UVEN is low or the internal UVLO or POR are active. The TIMER pin should be tied to ground if this

feature is not used.

8

Submit Documentation Feedback

Copyright © 2010, Texas Instruments Incorporated

Product Folder Link(s): TPS2492 TPS2493