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AD5749ACPZ Datasheet(PDF) 4 Page - Analog Devices |
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AD5749ACPZ Datasheet(HTML) 4 Page - Analog Devices |
4 / 28 page AD5749 Rev. 0 | Page 4 of 28 Parameter1 Min Typ Max Unit Test Conditions/Comments OUTPUT CHARACTERISTICS2 Current Loop Compliance Voltage 0 AVDD − 2.75 V Resistive Load Chosen such that compliance is not exceeded Inductive Load See the Test Conditions/ Comments column H Needs appropriate capacitor at higher inductance values; see the Driving Inductive Loads section Settling Time 4 mA to 20 mA, Full-Scale Step 8.5 μs 250 Ω load 120 μA Step, 4 mA to 20 mA Range 1.2 μs 250 Ω load DC PSRR 1 μA/V Output Impedance 130 MΩ DIGITAL INPUTS2 JEDEC compliant Input High Voltage, VIH 2 V Input Low Voltage, VIL 0.8 V Input Current −1 +1 μA Per pin Pin Capacitance 5 pF Per pin DIGITAL OUTPUTS2 FAULT, IFAULT, TEMP, VFAULT VOL, Output Low Voltage 0.4 V 10 kΩ pull-up resistor to DVCC 0.6 V At 2.5 mA VOH, Output High Voltage 3.6 V 10 kΩ pull-up resistor to DVCC SDO VOL, Output Low Voltage 0.5 0.5 V Sinking 200 μA VOH, Output High Voltage DVCC − 0.5 DVCC − 0.5 V Sourcing 200 μA High Impedance Output Capacitance 3 pF High Impedance Leakage Current −1 +1 μA POWER REQUIREMENTS AVDD 10.8 55 V DVCC Input Voltage 2.7 5.5 V AIDD 4.4 5.6 mA Output unloaded, output disabled; R3, R2, R1, R0 = 0000, RSET = 0 5.2 6.2 mA Output enabled DICC 0.3 1 mA VIH = DVCC, VIL = GND Power Dissipation 108 mW AVDD = 24 V, output unloaded 1 Temperature range: −40°C to +105°C; typical at +25°C. 2 Guaranteed by design and characterization, not production tested. |
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