Preliminary Technical Data

AD5755/AD5735

Rev. PrG | Page 25 of 34

Table 30. Software Register Functions

User Program Bit

This bit is mapped to bit D11 of the Status Register. When this bit is set to 1 bit D11 of the Status Register is set to

1. Likewise when D12 is set to 0 bit D11 of the Status Register is also set to zero. This feature can be used to

ensure the SPI pins are working correctly by writing known bit to this register and reading back corresponding

bit from the Status Register.

RESET CODE/SPI CODE

Option

Description

RESET CODE

Writing 0x555 to D11-D0 performs a reset.

SPI CODE

If Watchdog Timer feature enabled, 0x195 must be written to the Software Register

(D11-D0) within every timeout period to ensure valid data communication path.

DC-DC CONTROL REGISTER

The DC-DC Control Register allows the user control over the DC-DC Switching Frequency, and of the phase of when the per channel

switching starts. The maximum allowable DC-DC output frequency is also programmable.

Table 31. Programming the DC-DC Control Register

MSB

LSB

D15

D14

D13

D12 to D7

D5 to D4

D3 to D2

D1 to D0

0

1

1

X

DC-DC Phase

DC-DC Freq

DC-DC MaxV

Table 32. DC-DC Control Register Options

Option

Description

DC-DC Phase

User Programmable DC-DC Phase (Between Channels)

00 = All DC-DCs clock on same edge

01 = ChanA, ChanB clock on same edge, ChanC & ChanD clock on opposite edge

10 = ChanA, ChanC clock on same edge, ChanB & ChanD on opposite edge

11 = ChanA, ChanB, ChanC, ChanD clock 90' out of phase from each other

DC-DC Freq

User Programmable DC-DC Switching Frequency:

00 = 250 Khz

01 = 406 Khz

10 = 649 Khz

11 = 812 Khz

DC-DCMaxV

00 = 25V ±1V

01 = 27.3 ±1V

10 = 28.6 ±1V

11 = 30 ±1V

SLEW RATE CONTROL REGISTER

This register is used to program the slew rate control for the selected DAC Channel. The CREG bits are set to ‘0,0,0’ to select the Slew

Rate Control Register. SR_CLOCK and SR_STEP allow the user to control the rate of the output SLEW. This feature is available on both

the current and voltage outputs. With the slew rate control feature disabled the output value will change at a rate limited by the output

drive circuitry and the attached load. SE enables output slew rate control. It can be both programmed and enabled/disabled on a per

channel basis. For more information see the features section.

Table 33. Programming the Slew Rate Control Register

D15

D14

D13

D12

D11-D7

D6 to D3

D2 to D0

0

0

0

SE

X

SR_CLOCK

SR_STEP