AD9650-25EBZ datasheet(1/44 Pages) AD

Part #	AD9650-25EBZ

Description	16-Bit, 25 MSPS/65 MSPS/80 MSPS/105 MSPS, 1.8 V Dual Analog-to-Digital Converter (ADC)

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16-Bit, 25 MSPS/65 MSPS/80 MSPS/105 MSPS,

1.8 V Dual Analog-to-Digital Converter (ADC)

AD9650

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibilityis assumedbyAnalogDevicesforitsuse,norforanyinfringements of patents or other

rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

www.analog.com

Fax: 781.461.3113

FEATURES

1.8 V analog supply operation

1.8 V CMOS or LVDS output supply

SNR

82 dBFS at 30 MHz input and 105 MSPS data rate

83 dBFS at 9.7 MHz input and 25 MSPS data rate

SFDR

90 dBc at 30 MHz input and 105 MSPS data rate

95 dBc at 9.7 MHz input and 25 MSPS data rate

Low power

328 mW per channel at 105 MSPS

119 mW per channel at 25 MSPS

Integer 1-to-8 input clock divider

IF sampling frequencies to 300 MHz

Analog input range of 2.7 V p-p

Optional on-chip dither

Integrated ADC sample-and-hold inputs

Differential analog inputs with 500 MHz bandwidth

ADC clock duty cycle stabilizer

APPLICATIONS

Industrial instrumentation

X-Ray, MRI, and ultrasound equipment

High speed pulse acquisition

Chemical and spectrum analysis

Direct conversion receivers

Multimode digital receivers

Smart antenna systems

General-purpose software radios

GENERAL DESCRIPTION

The AD9650 is a dual, 16-bit, 25 MSPS/65 MSPS/80 MSPS/

105 MSPS analog-to-digital converter (ADC) designed for

digitizing high frequency, wide dynamic range signals with

input frequencies of up to 300 MHz.

The dual ADC core features a multistage, differential pipelined

architecture with integrated output error correction logic. Each

ADC features wide bandwidth, differential sample-and-hold

analog input amplifiers, and shared integrated voltage reference,

which eases design considerations. A duty cycle stabilizer is

provided to compensate for variations in the ADC clock duty

cycle, allowing the converters to maintain excellent performance.

The ADC output data can be routed directly to the two external

16-bit output ports or multiplexed on a single 16-bit bus. These

outputs can be set to either 1.8 V CMOS or LVDS.

FUNCTIONAL BLOCK DIAGRAM

CMOS/LVDS

OUTPUT BUFFER

CMOS/LVDS

OUTPUT BUFFER

ADC

DRVDD

CSB

AVDD

SPI

SDIO/

DCS

SCLK/

DFS

PROGRAMMING DATA

DUTY CYCLE

STABILIZER

DIVIDE 1

TO 8

DCO

GENERATION

REF

SELECT

MULTICHIP

SYNC

AGND

NOTES

1. PIN NAMES ARE FOR THE CMOS PIN CONFIGURATION ONLY;

SEE FIGURE 7 FOR LVDS PIN NAMES.

PDWN

OEB

DCOB

DCOA

D15A (MSB)

TO

D0A (LSB)

D15B (MSB)

TO

D0B (LSB)

ORA

CLK–

CLK+

ORB

VIN+A

VCM

RBIAS

VIN–B

VIN+B

VIN–A

VREF

SENSE

AD9650

ADC

16

Figure 1.

Flexible power-down options allow significant power savings,

when desired.

Programming for setup and control is accomplished using a 3-wire

SPI-compatible serial interface.

The AD9650 is available in a 64-lead LFCSP and is specified over

the industrial temperature range of −40°C to +85°C.

PRODUCT HIGHLIGHTS

1.

On-chip dither option for improved SFDR performance

with low power analog input.

2.

Proprietary differential input that maintains excellent SNR

performance for input frequencies up to 300 MHz.

3.

Operation from a single 1.8 V supply and a separate digital

output driver supply accommodating 1.8 V CMOS or

LVDS outputs.

4.

Standard serial port interface (SPI) that supports various

product features and functions, such as data formatting

(offset binary, twos complement, or gray coding), enabling

the clock DCS, power-down, and test modes.

5.

Pin compatible with the AD9268 and other dual families,

AD9269, AD9251, AD9231, and AD9204. This allows a

simple migration across resolutions and bandwidth.

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