OUT(CL)

IN(DC)

I

= (1 D)

I

-

g

IN

OUT

V

D

1

V

h

=

-

g

TPS61251

SLVSAF7 – SEPTEMBER 2010

www.ti.com

DETAILED DESCRIPTION

OPERATION

The TPS61251 Boost Converter operates as a quasi-constant frequency adaptive on-time controller. In a typical

application the frequency will be 3.5 MHz and is defined by the input to output voltage ratio and does not vary

from moderate to heavy load currents. At light load the converter will automatically enter Power Save Mode and

operates in PFM (Pulse Frequency Modulation) mode. During PWM operation the converter uses a unique fast

response quasi-constant on-time valley current mode controller scheme which offers excellent line and load

regulation and the use of small ceramic input capacitors.

cycle, the low-side NMOS switch is turned-on and the inductor current ramps up to a peak current that is defined

by the on-time and the inductance. In the second phase, once the peak current is reached, the current

comparator trips, the on-timer is reset turning off the switch, and the current through the inductor then decays to

an internally set valley current limit. Once this occurs, the on-timer is set to turn the boost switch back on again

and the cycle is repeated.

The TPS61251 directly and accurately controls the average input current through intelligent adjustment of the

valley current limit, allowing an accuracy of ±10%. Together with an external bulk capacitor the TPS61251 allows

an application to be interfaced directly to its load, without overloading the input source due to appropriate set

average input current limit .

High values of output capacitance are mainly achieved by putting capacitors in parallel. This reduces the overall

series resistance (ESR) to very low values. This results in almost no voltage ripple at the output and therefore

the regulation circuit has no voltage drop to react on. Nevertheless to guarantee accurate output voltage

regulation even with very low ESR the regulation loop can switch to a pure comparator regulation scheme.

During this operation the output voltage is regulated between two thresholds. The upper threshold is defined by

the programmed output voltage and the lower value is about 10 mV lower. If the upper threshold is reached the

off-time is increased to reduce the current in the inductor. Therefore the output voltage will slightly drop until the

lower threshold is tripped. Now the off-time will be reduced to increase the current in the inductor to charge up

the output voltage to the steady-state value. The current swing during this operation mode is strongly depending

on the current drawn by the load but will not exceed the programmed current limit. The output voltage during

comparator operation stays within the specified accuracy with minimum voltage ripple.

This architecture with adaptive slope compensation provides excellent transient load response and requiring

minimal output filtering. Internal softstart and loop compensation simplifies the design process while minimizing

the number of external components.

CURRENT LIMIT OPERATION

The current limit circuit employs a valley current sensing scheme. Current limit detection occurs during the

off-time through sensing of the voltage drop across the synchronous rectifier. The output voltage is reduced as

the power stage of the device operates in a constant current mode. The maximum continuous output current

(1)

The duty cycle (D) can be estimated by following Equation 2

(2)

SOFTSTART

The TPS61251 has an internal charging circuit that controls the current during the output capacitor charging and

prevents the converter from inrush current that exceeds the set current limit. For typical 100 µs the current is

ramped to the set current limit. After reaching the current limit threshold the output capacitor is charged with a

rectifying switch is controlled by the current limit circuit and works as a linear regulator in constant current mode.

10

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