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ISL6261CRZ Datasheet(PDF) 11 Page - Intersil Corporation |
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ISL6261CRZ Datasheet(HTML) 11 Page - Intersil Corporation |
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11 / 34 page  11 FN9251.1 September 27, 2006 Theory of Operation The ISL6261 is a single-phase regulator implementing Intel® IMVP-6® protocol and includes an integrated gate driver for reduced system cost and board area. The ISL6261 IMVP-6® solution provides optimum steady state and transient performance for microprocessor core voltage regulation applications up to 25A. Implementation of diode emulation mode (DEM) operation further enhances system efficiency. The heart of the ISL6261 is the patented R3 Technology™, Intersil’s Robust Ripple Regulator modulator. The R3™ modulator combines the best features of fixed frequency and hysteretic PWM controllers while eliminating many of their shortcomings. The ISL6261 modulator internally synthesizes an analog of the inductor ripple current and uses hysteretic comparators on those signals to establish PWM pulses. Operating on the large-amplitude and noise-free synthesized signals allows the ISL6261 to achieve lower output ripple and lower phase jitter than either conventional hysteretic or fixed frequency PWM controllers. Unlike conventional hysteretic converters, the ISL6261 has an error amplifier that allows the controller to maintain 0.5% voltage regulation accuracy throughout the VID range from 0.75V to 1.5V. The hysteretic window voltage is with respect to the error amplifier output. Therefore the load current transient results in increased switching frequency, which gives the R3™ regulator a faster response than conventional fixed frequency PWM regulators. Start-up Timing With the controller’s VDD pin voltage above the POR threshold, the start-up sequence begins when VR_ON exceeds the 3.3V logic HIGH threshold. In approximately 100 μs, SOFT and VO start ramping to the boot voltage of 1.2V. At startup, the regulator always operates in continuous current mode (CCM), regardless of the control signals. During this interval, the SOFT cap is charged by a 41 μA current source. If the SOFT capacitor is 20nF, the SOFT ramp will be 2mV/ μs for a soft-start time of 600μs. Once VO is within 10% of the boot voltage and PGD_IN is HIGH for six PWM cycles (20µs for 300kHz switching frequency), CLK_EN# is pulled LOW, and the SOFT cap is charged/discharged by approximate 200µA and VO slews at 10mV/ μs to the voltage set by the VID pins. In approximately 7ms, PGOOD is asserted HIGH. Figure 4 shows typical startup timing. PGD_IN Latch It should be noted that PGD_IN going low will cause the converter to latch off. Toggling PGD_IN won’t clear the latch. Toggling VR_ON will clear it. This feature allows the converter to respond to other system voltage outages immediately. Static Operation After the startup sequence, the output voltage will be regulated to the value set by the VID inputs per Table 1, which is presented in the lntel® IMVP-6® specification. The ISL6261 regulates the output voltage with ±0.5% accuracy over the range of 0.7V to 1.5V. A true differential amplifier remotely senses the core voltage to precisely control the voltage at the microprocessor die. VSEN and RTN pins are the inputs to the differential amplifier. As the load current increases from zero, the output voltage droops from the VID value proportionally to achieve the IMVP-6® load line. The ISL6261 can sense the inductor current through the intrinsic series resistance of the inductors, as shown in Figure 2, or through a precise resistor in series with the inductor, as shown in Figure 3. The inductor current information is fed to the VSUM pin, which is the non-inverting input to the droop amplifier. The DROOP pin is the output of the droop amplifier, and DROOP-VO voltage is a high-bandwidth analog representation of the inductor current. This voltage is used as an input to a differential amplifier to achieve the IMVP-6® load line, and also as the input to the overcurrent protection circuit. When using inductor DCR current sensing, an NTC thermistor is used to compensate the positive temperature coefficient of the copper winding resistance to maintain the load-line accuracy. The switching frequency of the ISL6261 controller is set by the resistor RFSET between pins VW and COMP, as shown in Figures 2 and 3. VDD VR_ON SOFT &VO PGD_IN CLK_EN# IMVP-VI PGOOD ~20us 100us Vboot 2mV/us 10mV/us ~7ms FIGURE 4. SOFT-START WAVEFORMS USING A 20nF SOFT CAPACITOR ISL6261 |
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