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HSP50210JI-52 Datasheet(PDF) 8 Page - Intersil Corporation |
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HSP50210JI-52 Datasheet(HTML) 8 Page - Intersil Corporation |
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8 / 51 page  FN3652.5 July 2, 2008 8 NCO/Mixer The NCO/Mixer performs a complex multiply between the baseband input and the output of a quadrature NCO (Numerically Controlled Oscillator). When the HSP50210 (DQT) is used with the HSP50110 (DCL), the NCO/Mixer shortens the Carrier Tracking Loop (i.e., minimizes pipeline delay around the loop) while providing wide loop bandwidths. This becomes important when operating at symbol rates near the maximum range of the part. There are three configurations possible for closing the Carrier Tracking Loop when the DQT and the DCL are used together. The first configuration utilizes the NCO on the DQT and bypasses the NCO in the DCL. The Data Path Configuration Control Register (see Table 15 on page 32), Bit 10, and Carrier Loop Filter Control Register #1 (see Table 21 on page 34), Bit 6, are used to bypass the DCL NCO/Mixer and route the Loop filter outputs, respectively. The DQT provides maximum flexibility in NCO control with respect to frequency and phase offsets. The second configuration feeds the lead Carrier Loop filter term to the DCL NCO/Mixer, and the lag Loop filter Term to the DQT NCO. This reduces the loop transport delay while maintaining wide loop bandwidths and reasonable loop damping factors. This configuration is especially useful in SATCOM applications with medium to high symbol rates. The Carrier Loop Filter Control Register #1, Bit 5 is where the lead/lag destination is set. The final configuration feeds both the lead and lag Carrier Loop Filter terms back to the DCL NCO/Mixer. This provides the shortest transport delay. The DCL NCO/Mixer provides only for frequency/phase control from the Carrier Loop filter. The center frequency of this NCO/Mixer is set to the average of the Upper and Lower Carrier Loop Limits programmable parameters. These parameters are set in the two control registers bearing their names (see Tables 23 and 24 on page 35). The NCO/Mixer uses a complex multiplier to multiply the baseband input by the output of a quadrature NCO. This operation is represented by Equations 2 and 3: Equation 3 illustrates how the complex multiplier implicitly performs the summing function when the DCL is configured as a modulator. The quadrature outputs of the NCO are generated by driving a sine/cosine look-up table with the output of a phase accumulator, as shown in Figure 3 on page 7. Each time the phase accumulator is clocked, its sum is incremented by the contents of the Carrier Frequency (CF) Register. As the accumulator sum increments from 0 to 232, the SIN/COS ROM produces quadrature outputs whose phase advances from 0 to 360°. The CF Register contains a 32-bit phase increment, which is updated with the output of Carrier Tracking Loop. Large phase increments take fewer clocks to step through the sine wave cycle, which results in a higher frequency NCO output. The CF Register sets the NCO frequency using Equation 4: where fCLK is the CLK frequency, and CF is the 32-bit two’s complement hexadecimal value loaded into the Carrier Frequency Register. As an example, if the CF Register is loaded with a value of 4000 0000 (Hex), and the CLK frequency is 40MHz, the NCO would produce quadrature terms with a frequency of 10MHz. When CF is a negative value, a clockwise cos/sin vector rotation is produced. When CF is positive, a counterclockwise vector rotation is produced. Note: The NCO is set to a fixed frequency by programming the upper and lower limits of the Carrier Tracking Loop Filter to the same value and zeroing the lead gain. Matched Filtering The HSP50210 provides two selectable matched filters: a Root Raised Cosine Filter (RRC) and an Integrate and Dump (I and D) filter. These are shown in Figure 3. The RRC filter is provided for shaped data pulses and the I and D filter is provided for square wave data. The filters may be cascaded for better adjacent channel rejection for square wave data. If these two filters do not meet baseband filtering requirements, then they can be bypassed and an external digital filter (such as the HSP43168 Dual FIR Filter or the HSP43124 Serial I/O Filter) used to implement the desired matched filter. The desired filter configuration is set in the Data Path Configuration Control Register, bits 1 through 7 (see Table 15 on page 32). The sample rate of the baseband input depends on the symbol rate and filtering configuration chosen. In configurations which bypass both filters or use only the RRC Filter, the input sample rate must be twice the symbol rate. In configurations which use the I and D Filter, the input sample rate is decimated by the I and D Filter, down to two samples per symbol. I and D configurations support input sample rates up to 32x the input symbol rate. The RRC filter is a fixed coefficient 15 Tap FIR filter. It has ~40% excess bandwidth beyond Nyquist, which equates to α = ~0.4 shape factor. The filter frequency response is shown in Figures 4 and 5. In addition, the 9-bit filter coefficients are listed as integer values in Table 1. The noise equivalent bandwidth of the RRC filter and other filter configurations possible with the HSP50110/210 chipset are given in Appendix A. I OUT I IN ω C () cos Q IN ω C () sin – = Q OUT I IN ω C () sin Q IN ω C () cos + = (EQ. 2) (EQ. 3) F C f CLK CF () 2 ⁄ 32 × = CF INT F C fCLK ⁄ ()2 32 []H = (EQ. 4) HSP50210 |
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