10

FN2486.10

October 10, 2008

Coefficient RAM

The Coefficient RAM stores the coefficients for the current FIR

filter being implemented. The coefficients are loaded into the

Coefficient RAM over the control bus (C_BUS). The

coefficients are written into the Coefficient RAM sequentially,

starting at location zero. It is only necessary to write one half

of the coefficients when symmetric filters are being

implemented, where the last coefficient to be written in is the

center tap.

The coefficients are loaded into address 01 in two writes.

The first write loads the upper 16 bits of the 20-bit coefficient,

C4 through C19. The second write loads the lower 4 bits of

the coefficient, C0 through C3, where C19 is the MSB. The

two 16-bit writes are then formatted into the 20-bit coefficient

that is then loaded into the Coefficient RAM starting at RAM

address location zero, where the coefficient at this location is

the outer tap (or the first coefficient value).

To reload coefficients, the Coefficient RAM Address pointer

must be reset to location zero so that the coefficients will be

loaded in the order the FIR filter expects. There are two

methods that can be used to reset the Coefficient RAM

address pointer. The first is to assert RESET, which

automatically resets the pointer, but also clears the HDF and

alters some of the control register bits. (RESET does not

change any of the coefficient values.) The second method is

to set the F_DIS bit in control register H_ REGISTER1. This

control bit allows any of the FIR control register bits to be re-

programmed, but does not automatically modify any control

registers. When the programming is completed, the FIR is

re-started by clearing the F_DIS bit or by asserting one of

the start inputs (ASTARTIN or STARTIN). The F_DIS bit

allows the filter parameters to be changed more quickly and

is thus the recommended reprogramming method.

Data RAM

The Data RAM stores the data needed for the filter

calculation. The format of the data is:

The 16-bit output of the HDF Output Register is written into

the Data Ram on the rising edge of CK_DEC.

RESET initializes the write pointer to the data RAM. After a

RESET occurs, the output of the FIR will not be valid until

the number of new data samples written to the Data RAM

equals TAPS.

The filter always operates on the most current sample and

the taps-1 previous samples. Thus if the F_DIS bit is set,

data continues to be written into the data RAM coming from

the HDF section. When the FIR is enabled again the filter will

be operating on the most current data samples and thus

another transient response will not occur.

The maximum throughput of the FIR filter is limited by the

use of a single Multiplier/Accumulator (MAC). The data

output from the HDF being clocked into the FIR filter by

CK_DEC must not be at a rate that causes an erroneous

result being calculated because data is being overwritten.

Equation 2 describes the relationship between, FIR_CK,

CK_DEC, the number of taps that can be implemented in the

FIR, the decimation rate in the HDF and the decimation rate

in the FIR. (In the Design Considerations section of the

“Operational Section” on page 12 there is a chart that shows

the tradeoffs between these parameters.)

This equation expresses the minimum FIR_CK. The

minimum FIR_CK is the smallest integer multiple of CK_IN

that satisfies Equation 1. In addition, the TSK specification

TAPS = the number of taps in the FIR for even length filters

and equals the number of taps+1 for odd length filters.

Solving Equation 3 for the maximum number of taps:

In using this equation, it must be kept in mind that CK_IN/

is in bypass mode in which case this limitation in the HDF

does not apply). In the “Operational Section” on page 12

under the Design Considerations, there is a table that shows

the trade-offs of these parameters. In addition, Intersil

provides a software package called DECIMATE™ which

designs the DDF filter from System specifications.

The registered outputs of the data RAM are added or

subtracted in the 17-bit pre-adder. The F_OAD control bit

allows zeros to be input into one side of the pre-adder. This

provides the capability to implement non-symmetric filters.

The selection of adding the register outputs for an even

symmetric filter or for subtracting the register outputs for odd

symmetric filter is provided by the control bit F_ESYM, which

is programmed over the control bus. When subtraction is

selected, the new data is subtracted from the old data. The

17-bit output of the adder forms one input of the

multiplier/accumulator.

A control bit F_CLA provides the capability to clear the

feedback path in the accumulator such that multiplier output will

not be accumulated, but will instead flow directly to the output

register. The bit weightings of the data and coefficients as they

are processed in the FIR is shown as follows.

Input Data (from HDF)

Pre-adder Output

Coefficient

Accumulator

FIR_CK

CK_IN TAPS/2

() 4F

DEC

++

[]

H

----------------------------------------------------------------------------------

≥

(EQ. 2)

TAPS

2

FIR_CK H

CK_IN

----------------------------------------------------------

F

–

⎝⎠

⎛⎞

=

(EQ. 3)

HSP43220