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ISL6263BHRZ Datasheet(PDF) 9 Page - Intersil Corporation |
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ISL6263BHRZ Datasheet(HTML) 9 Page - Intersil Corporation |
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9 / 18 page  9 FN6388.3 July 8, 2010 Theory of Operation The R3 Modulator The heart of the ISL6263B is Intersil’s Robust-Ripple- Regulator (R3) Technology™. The R3 modulator is a hybrid of fixed frequency PWM control, and variable frequency hysteretic control that will simultaneously affect the PWM switching frequency and PWM duty cycle in response to input voltage and output load transients. The term “Ripple” in the name “Robust-Ripple-Regulator” refers to the synthesized voltage-ripple signal VR that appears across the internal ripple-capacitor CR. The VR signal is a representation of the output inductor ripple current. Transconductance amplifiers measuring the input voltage of the converter and the output set-point voltage VSOFT, together produce the voltage-ripple signal VR. A voltage window signal VW is created across the VW and COMP pins by sourcing a current proportional to gmVsoft through a parallel network consisting of resistor RFSET and capacitor CFSET. The synthesized voltage-ripple signal VR along with similar companion signals are converted into PWM pulses. The PWM frequency is proportional to the difference in amplitude between VW and VCOMP. Operating on these large-amplitude, low noise synthesized signals allows the ISL6263B to achieve lower output ripple and lower phase jitter than either conventional hysteretic or fixed frequency PWM controllers. Unlike conventional hysteretic converters, the ISL6263B has an error amplifier that allows the controller to maintain tight voltage regulation accuracy throughout the VID range from 0.41200V to 1.28750V. Power-On Reset The ISL6263B is disabled until the voltage at the VDD pin has increased above the rising VDD power-on reset (POR) VDD_THR threshold voltage. The controller will become disabled when the voltage at the VDD pin decreases below the falling POR VDD_THF threshold voltage. Start-Up Timing Figure 4 shows the ISL6263B start-up timing. Once VDD has ramped above VDD_THR, the controller can be enabled by pulling the VR_ON pin voltage above the input-high threshold VVR_ONH. Approximately 100µs later, the soft-start capacitor CSOFT begins slewing to the designated VID set-point as it is charged by the soft-start current source ISS. The VCCGFX output voltage of the converter follows the VSOFT voltage ramp to within 10% of the VID set-point then counts 13 switching cycles, then changes the open-drain output of the PGOOD pin to high impedance. During soft-start, the regulator always operates in continuous conduction mode (CCM). TABLE 2. VID TABLE FOR INTEL IMVP-6+ VCCGFX CORE VID4 VID3 VID2 VID1 VID0 VCCGFX (V) -- -- - 0 0 0 0 0 0 1.28750 0 0 0 0 1 1.26175 0 0 0 1 0 1.23600 0 0 0 1 1 1.21025 0 0 1 0 0 1.18450 0 0 1 0 1 1.15875 0 0 1 1 0 1.13300 0 0 1 1 1 1.10725 0 1 0 0 0 1.08150 0 1 0 0 1 1.05575 0 1 0 1 0 1.03000 0 1 0 1 1 1.00425 0 1 1 0 0 0.97850 0 1 1 0 1 0.95275 0 1 1 1 0 0.92700 0 1 1 1 1 0.90125 1 0 0 0 0 0.87550 1 0 0 0 1 0.84975 1 0 0 1 0 0.82400 1 0 0 1 1 0.79825 1 0 1 0 0 0.77250 1 0 1 0 1 0.74675 1 0 1 1 0 0.72100 1 0 1 1 1 0.69525 1 1 0 0 0 0.66950 1 1 0 0 1 0.64375 1 1 0 1 0 0.61800 1 1 0 1 1 0.59225 1 1 1 0 0 0.56650 1 1 1 0 1 0.54075 1 1 1 1 0 0.51500 1 1 1 1 1 0.41200 ISL6263B |
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