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ISL6540AIRZA Datasheet(PDF) 11 Page - Intersil Corporation |
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ISL6540AIRZA Datasheet(HTML) 11 Page - Intersil Corporation |
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11 / 22 page  11 FN6288.5 October 7, 2008 OV/UV/PGOOD comparators. The VMON pin should be connected to the FB pin by a standard feedback network. In the event of the remote sense buffer is disabled, the VMON pin should be connected to VOUT by a resistor divider along with FB’s compensation network. An RC filter should be used if VMON is to be connected directly to FB instead of to VOUT through a separate resistor divider network. GND (Bottom Side Pad, Analog Ground) Signal ground for the IC. All voltage levels are measured with respect to this pin. This pin should not be left floating. Functional Description Initialization The ISL6540A automatically initializes upon receipt of power without requiring any special sequencing of the input supplies. The Power-On Reset (POR) function continually monitors the input supply voltages (PVCC, VFF, VCC) and the voltage at the EN pin. Assuming the EN pin is pulled to above ~0.50V, the POR function initiates soft-start operation after all input supplies exceed their POR thresholds. With all input supplies above their POR thresholds, driving the EN pin above 0.50V initiates a soft-start cycle. In addition to normal TTL logic, the enable pin can be used as a voltage monitor with programmable hysteresis through the use of the internal 10µA sink current and an external resistor divider. This feature is especially designed for applications that have input rails greater than a 3.3V and require a specific input rail POR and Hysteresis levels for better undervoltage protection. Consider for a 12V application choosing RUP =97.6kΩ and RDOWN = 5.76kΩ there by setting the rising threshold (VEN_RTH) to ~10V and the falling threshold (VEN_FTH) to ~9V, for ~1V of hysteresis (VEN_HYS). Care should be taken to prevent the voltage at the EN pin from exceeding VCC when using the programmable UVLO functionality. Soft-Start The POR function activates the internal 37µA OTA which begins charging the external capacitor (CSS) on the SS pin to a target voltage of VCC. The ISL6540A’s soft-start logic continues to charge the SS pin until the voltage on COMP exceeds the bottom of the oscillator ramp, at which point, the driver outputs are enabled with the low side MOSFET first being held low for 200ns to provide for charging of the bootstrap capacitor. Once the driver outputs are enabled, the OTA’s target voltage is then changed to the margined (if margining is being used) reference voltage (VREF_MARG), and the SS pin is ramped up or down accordingly. This method reduces start-up surge currents due to a pre-charged output by inhibiting regulator switching until the control loop enters its linear region. By ramping the positive input of the error amplifier to VCC and then to VREF_MARG, it is even possible to mitigate surge currents from outputs that are pre-charged above the set output voltage. As the SS pin connects directly to the non-inverting input of the error amplifier, noise on this pin should be kept to a minimum through careful routing and part placement. To prevent noise injection into the error amplifier the SS capacitor should be located within 150 mils of the SS and GND pins. Soft-start is declared done when the drivers have been enabled and the SS pin is within ±3mV of VREF_MARG. VCC POR PVCC POR VFF POR EN POR SOFT-START HIGH = ABOVE POR; LOW = BELOW POR AND FIGURE 1. SOFT-START INITIALIZATION LOGIC VEN_REF IEN_HYS=10µA 1k Ω RDOWN VIN R UP V EN_HYS I EN_HYS -------------------------- 1k Ω – = R DOWN R UP 1k Ω + () V • EN_REF V EN_FTH V EN_REF – ------------------------------------------------------------------ = V EN_FTH V EN_RTH V EN_HYS – = SYS_ENABLE FIGURE 2. ENABLE POR CIRCUIT RUP EN REN FIGURE 3. UNDERVOLTAGE-OVERVOLTAGE WINDOW -15% -9% VREF_MARG +9% +15% VMON UV UV OV GOOD GOOD T PG_DLY C PG_DLY 1.49V 21 μA ---------------- ⋅ = (EQ. 1) ISL6540A |
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