11

FN7442.3

September 8, 2005

Applications Information

Video In

A simplified block diagram is shown following page.

nominally 0.1µF. Clamp charge current will prevent the

signal on pin 2 from going any more negative than Sync Tip

Ref, about 1.5V. This charge current is nominally about 1mA.

A clamp discharge current of about 10µA is always

lost between sync pulses that must be replaced during sync

pulses. The droop voltage that will occur can be calculated

from IT = CV, where V is the droop voltage, I is the discharge

current, T is the time between sync pulses (sync period -

An NTSC video signal has a horizontal frequency of

15.73kHz, and a sync tip width of 4.7µs. This gives a period

of 63.6µs and a time T = 58.9µs. The droop voltage will then

be V = 5.9mV. This is less than 2% of a nominal sync tip

amplitude of 286mV. The charge represented by this droop

is replaced in a time given by T = CV/I, where I = clamp

charge current = 5.3mA. Here T = 590ns, about 12% of the

enough so that the droop voltage does not approach the

switching threshold of the internal comparator.

Composite Sync

The Composite Sync output is simply a reproduction of the

input signal with the active video removed. The sync tip of

the Composite video signal is clamped to 1.5V at pin 2 and

then slices at 70mV above the sync tip reference. The output

signal is buffered out to pin 1. When loss of sync, the

Composite Sync output is held low.

Vertical Sync

A low-going Vertical Sync pulse is output during the start of

the vertical cycle of the incoming video signal. The vertical

cycle starts with a pre-equalizing phase of pulses with a duty

cycle of about 93%, followed by a vertical serration phase

that has a duty cycle of about 15%. Vertical Sync is clocked

out of the ISL59885 on the first rising edge during the

vertical serration phase. In the absence of vertical serration

pulses, a vertical sync pulse will be forced out after the

vertical sync default delay time, approximately 60µs after the

last falling edge of the vertical equalizing phase.

Horizontal Sync

The horizontal circuit senses the composite sync edges and

produces the true horizontal pulses of nominal width 5.2µs.

The leading edge is triggered from the leading edge of the

input H sync, with the same propagation delay as composite

sync. The half line pulses present in the input signal during

vertical blanking are removed with an internal 2H line

eliminator circuit. This is a circuit that inhibits horizontal

output pulses until 75% of the line time is reached, then the

horizontal output operation is enabled again. Any signals

present on the I/P signal after the true H sync will be ignored,

thus the horizontal output will not be affected by MacroVision

copy protection. When loss of sync, the Horizontal Sync

output is held high.

the Y5U general use capacitors may be too leaky and cause

Chroma Filter

A chroma filter is suggested to increase the S/N ratio of the

incoming video signal. Use of the optional chroma filter is

shown in the figure below. It can be implemented very simply

and inexpensively with a series resistor of 100

Ω and a

capacitor of 570pF, which gives a single pole roll-off

frequency of about 2.79MHz during NTSC or PAL. This

sufficiently attenuates the 3.58MHz (NTSC) or 4.43MHz

(PAL) color burst signal, yet passes the approximately 15kHz

sync signals without appreciable attenuation. During HDTV,

the transistor turns off and a 100pF capacitor is left to filter

any noise present at the input. A chroma filter will increase

the propagation delay from the composite input to the

outputs.

HD-Detect

High definition video is flagged by HD going low when the

input horizontal frequency is greater than 20kHz.

ISL59885

0.1µF

100

Ω

470pF

VIDEO IN

CHROMA FILTER

1

2

3

4

8

7

6

5

HD

10k

Ω

MMBT3904

GND

100pF

ISL59885