10

FN9255.0

January 17, 2006

to the desired number). The higher the quality factor of the

regulator. Change the numerical factor (0.7) below to reflect

frequency helps reduce the gain of the compensation

network at high frequency, in turn reducing the HF ripple

component at the COMP pin and minimizing resultant duty

cycle jitter.

It is recommended that a mathematical model be used to

plot the loop response. Check the loop gain against the error

amplifier’s open-loop gain. Verify phase margin results and

adjust as necessary. The following equations describe the

COMPENSATION BREAK FREQUENCY EQUATIONS

Figure 8 shows an asymptotic plot of the DC/DC converter’s

gain vs. frequency. The actual Modulator Gain has a high gain

peak dependent on the quality factor (Q) of the output filter,

which is not shown. Using the above guidelines should yield a

compensation gain similar to the curve plotted. The open loop

error amplifier gain bounds the compensation gain. Check the

log-log graph of Figure 8 by adding the modulator gain,

dB). This is equivalent to multiplying the modulator transfer

function and the compensation transfer function and then

plotting the resulting gain.

A stable control loop has a gain crossing with close to a

-20dB/decade slope and a phase margin greater than 45

degrees. Include worst case component variations when

determining phase margin. The mathematical model

presented makes a number of approximations and is

generally not accurate at frequencies approaching or

exceeding half the switching frequency. When designing

compensation networks, select target crossover frequencies

in the range of 10% to 30% of the switching frequency,

Component Selection Guidelines

Output Capacitor Selection

An output capacitor is required to filter the output and supply

the load transient current. The filtering requirements are a

function of the switching frequency and the ripple current.

The load transient requirements are a function of the slew

rate (di/dt) and the magnitude of the transient load current.

These requirements are generally met with a mix of

capacitors and careful layout.

Modern microprocessors produce transient load rates above

1A/ns. High frequency capacitors initially supply the transient

and slow the current load rate seen by the bulk capacitors.

The bulk filter capacitor values are generally determined by

the ESR (effective series resistance) and voltage rating

requirements rather than actual capacitance requirements.

High frequency decoupling capacitors should be placed as

close to the power pins of the load as physically possible. Be

careful not to add inductance in the circuit board wiring that

could cancel the usefulness of these low inductance

C

1

1

2

π R

⋅⋅

⋅

-----------------------------------------------

=

C

2

C

1

2

π R

1

–

⋅⋅⋅

--------------------------------------------------------

=

R

3

R

1

F

SW

F

LC

------------ 1

–

----------------------

=

C

3

1

2

π R

⋅⋅

⋅

-------------------------------------------------

=

G

()

D

⋅

V

OSC

-------------------------------

1s f

() ESR C

⋅⋅

+

1s f

() ESR DCR

+

() C

⋅⋅

s

2

f

() LC

⋅⋅

++

-----------------------------------------------------------------------------------------------------------

⋅

=

G

()

1s f

() R

⋅⋅

+

sf

() R

1

C

1

C

2

+

()

⋅⋅

----------------------------------------------------

⋅

=

1s f

() R

1

R

3

+

() C

3

⋅⋅

+

1s f

() R

⋅⋅

+

() 1s f

() R

2

C

⋅

C

1

C

2

+

---------------------







⋅⋅

+







⋅

-------------------------------------------------------------------------------------------------------------------------

G

()

G

() G

()

⋅

=

where s f

()

,

2

π fj

⋅⋅

=

F

Z1

1

2

π R

⋅⋅

-------------------------------

=

F

Z2

1

2

π R

1

R

3

+

() C

3

⋅⋅

-------------------------------------------------

=

F

P1

1

2

π R

2

C

⋅

C

1

C

2

+

---------------------

⋅⋅

---------------------------------------------

=

F

P2

1

2

π R

⋅⋅

-------------------------------

=

0

OPEN LOOP E/A GAIN

COMPENSATION GAIN

FREQUENCY

MODULATOR GAIN

FIGURE 8. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN

CLOSED LOOP GAIN

20

D

MAX

V

⋅

IN

V

OSC

----------------------------------

log

20

R2

R1

--------





log

LOG

ISL6535