9

FN6481.0

April 24, 2008

• Shorten all gate drive loops (UGATE-PHASE and

LGATE-GND) and route them closely spaced.

• Minimize the inductance of the PHASE node. Ideally, the

source of the upper and the drain of the lower MOSFET

should be as close as thermally allowable.

• Minimize the current loop of the output and input power

trains. Short the source connection of the lower MOSFET

to ground as close to the transistor pin as feasible. Input

capacitors (especially ceramic decoupling) should be

placed as close to the drain of upper and source of lower

MOSFETs as possible.

• Avoid routing relatively high impedance nodes (such as

PWM and ENABLE lines) close to high dV/dt UGATE and

PHASE nodes.

In addition, for heat spreading, place copper underneath the

IC whether it has an exposed pad or not. The copper area

can be extended beyond the bottom area of the IC and/or

connected to buried power ground plane(s) with thermal

vias. This combination of vias for vertical heat escape,

extended copper plane, and buried planes for heat

spreading allows the IC to achieve its full thermal potential.

Upper MOSFET Self Turn-On Effects at Start-up

Should the driver have insufficient bias voltage applied, its

outputs are floating. If the input bus is energized at a high

dV/dt rate while the driver outputs are floating, due to the

UGATE could momentarily rise up to a level greater than the

threshold voltage of the MOSFET. This could potentially turn

on the upper switch and result in damaging inrush energy.

Therefore, if such a situation (when input bus powered up

before the bias of the controller and driver is ready) could

conceivably be encountered, it is a common practice to

upper MOSFET to suppress the Miller coupling effect. The

value of the resistor depends mainly on the input voltage’s

threshold of the upper MOSFET. A higher dV/dt, a lower

FET will require a smaller resistor to diminish the effect of

the internal capacitive coupling. For most applications, the

integrated 20k

Ω typically sufficient, not affecting normal

performance and efficiency.

The coupling effect can be roughly estimated with the

formulas in Equation 5, which assume a fixed linear input

ramp and neglect the clamping effect of the body diode of

the upper drive and the bootstrap capacitor. Other parasitic

components such as lead inductances and PCB

capacitances are also not taken into account. These

equations are provided for guidance purpose only.

Therefore, the actual coupling effect should be examined

using a very high impedance (10M

Ω or greater) probe to

ensure a safe design margin.

V

GS_MILLER

dV

dt

------- RC

V

–

DS

dV

dt

------- RC

⋅

iss

⋅

----------------------------------

–

⎝⎠

⎜⎟

⎜⎟

⎜⎟

⎜⎟

⎛⎞

⋅⋅

=

RR

UGPH

R

GI

+

=

C

rss

C

GD

=

C

iss

C

GD

C

GS

+

=

(EQ. 5)

FIGURE 5. GATE-TO-SOURCE RESISTOR TO REDUCE

UPPER MOSFET MILLER COUPLING

VIN

D

S

G

BOOT

DU

DL

PHASE

PVCC

UGATE

ISL6615