7

FN6494.0

April 25, 2008

Power-On Reset (POR) Function

During initial start-up, the VCC voltage rise is monitored. Once

the rising VCC voltage exceeds 3.8V (typically), operation of

the driver is enabled and the PWM input signal takes control

of the gate drives. If VCC drops below the falling threshold of

3.5V (typically), operation of the driver is disabled.

Internal Bootstrap Device

ISL6620, ISL6620A features an internal bootstrap Schottky

diode. Simply adding an external capacitor across the BOOT

and PHASE pins completes the bootstrap circuit. The

bootstrap function is also designed to prevent the bootstrap

capacitor from overcharging due to the large negative swing

at the trailing-edge of the PHASE node. This reduces

voltage stress on the BOOT to PHASE pins.

The bootstrap capacitor must have a maximum voltage

rating well above the maximum voltage intended for VCC. Its

capacitance value can be estimated using Equation 1:

control MOSFETs. The

ΔV

allowable droop in the rail of the upper gate drive. Select

results are exemplified in Figure 2.

Power Dissipation

Package power dissipation is mainly a function of the

layout resistance, and the selected MOSFET’s internal gate

dissipation in the driver for a desired application is critical to

ensure safe operation. Exceeding the maximum allowable

power dissipation level may push the IC beyond the maximum

recommended operating junction temperature. The DFN

package is more suitable for high frequency applications. See

“Layout Considerations” on page 8 for thermal impedance

improvement suggestions. The total gate drive power losses

due to the gate charge of MOSFETs and the driver’s internal

circuitry and their corresponding average driver current can

be estimated using Equations 2 and 3, respectively:

respectively; UVCC and LVCC are the drive voltages for

product is the quiescent power of the driver without a load.

The total gate drive power losses are dissipated among the

resistive components along the transition path, as outlined in

Equation 4. The drive resistance dissipates a portion of the

total gate drive power losses, the rest will be dissipated by the

the typical upper and lower gate drives turn-on current paths.

20nC

FIGURE 2. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE

VOLTAGE

ΔV

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0.0

0.3

0.0

0.1

0.2

0.4

0.5

0.6

0.9

0.7

0.8

1.0

50nC

C

BOOT_CAP

Q

GATE

ΔV

BOOT_CAP

--------------------------------------

≥

Q

GATE

Q

G1

VCC

•

V

GS1

-------------------------------

N

Q1

•

=

(EQ. 1)

FIGURE 3. TYPICAL UPPER-GATE DRIVE TURN-ON PATH

P

Qg_TOT

P

Qg_Q1

P

Qg_Q2

I

Q

VCC

•

++

=

(EQ. 2)

P

Qg_Q1

Q

G1

•

V

GS1

---------------------------------------

F

SW

•

N

Q1

•

=

P

Qg_Q2

Q

G2

•

V

GS2

--------------------------------------

F

SW

•

N

Q2

•

=

I

DR

Q

G1

UVCC

N

Q1

•

•

V

GS1

------------------------------------------------------

Q

G2

LVCC

N

Q2

•

•

V

GS2

-----------------------------------------------------

+

⎝⎠

⎜⎟

⎛⎞

F

SW

I

Q

+

•

=

(EQ. 3)

P

DR

P

DR_UP

P

DR_LOW

I

Q

VCC

•

++

=

(EQ. 4)

P

DR_UP

R

HI1

R

HI1

R

EXT1

+

--------------------------------------

R

LO1

R

LO1

R

EXT1

+

----------------------------------------

+

⎝⎠

⎜⎟

⎛⎞ P

Qg_Q1

2

---------------------

•

=

P

DR_LOW

R

HI2

R

HI2

R

EXT2

+

--------------------------------------

R

LO2

R

LO2

R

EXT2

+

----------------------------------------

+

⎝⎠

⎜⎟

⎛⎞ P

Qg_Q2

2

---------------------

•

=

R

EXT1

R

G1

R

GI1

N

Q1

-------------

+

=

R

EXT2

R

G2

R

GI2

N

Q2

-------------

+

=

Q1

D

S

G

BOOT

PHASE

UVCC

ISL6620, ISL6620A