7

FN6975.1

January 27, 2010

Application Information

Typical application schematic for ISL35111 is shown in Figure 8.

PCB Layout Considerations

Because of the high speed of the ISL35111 signals,

careful PCB layout is critical to maximize performance.

The following guidelines should be adhered to as closely

as possible:

• All high speed differential pair traces should have a

characteristic impedance of 50Ω with respect to

ground plane and 100Ω with respect to each other.

• Avoid using vias for high speed traces as this will

create discontinuity in the traces characteristic

impedance.

• Input and output traces need to have DC blocking

capacitors (100nF). Capacitors should be placed as

close to the chip as possible.

• For each differential pair, the positive trace and the

negative trace need to be of same length in order to

avoid intra-pair skew. Serpentine technique may be

used to match trace lengths.

• Maintain a constant solid ground plane underneath

the high-speed differential traces

bypassed to ground through a 47nF and a 100pF

capacitor in parallel. Minimize the trace length and

capacitors in order to maximize the power supply

noise rejection.

Intersil has long realized that to enable the complex

server clusters of next generation datacenters, it is

critical to manage the signal integrity issues of electrical

interconnects. To address this, Intersil has developed its

its analog ICs inside cabling interconnects, Intersil is able

to achieve unsurpassed improvements in reach, power

consumption, latency, and cable gauge size as well as

increased airflow in tomorrow's datacenters. This new

technology transforms passive cabling into intelligent

"roadways" that yield lower operating expenses and

capital expenditures for the expanding datacenter.

Intersil Lane Extenders allow greater reach over existing

cabling while reducing the need for thicker cables. This

significantly reduces cable weight and clutter, increases

airflow, and improves power consumption.

FIGURE 8. TYPICAL APPLICATION REFERENCE SCHEMATIC FOR ISL35111

NOTES:

12. See “Adjustable De-Emphasis” on page 6 for information on how to connect the DE pins

13. See “Line Silence/Quiescent Mode” on page 6 for details on DT pin operation.

TDSBL

DT

DEA

DEB

1.2V

1.2V

1.2V

47nF

47nF

ISL35111

IN_P

2

IN_N

3

VDD

1

VDD 9

VDD 12

OUT_N 10

OUT_P 11

TDSBL

4

100nF

100nF

100nF

100nF

100pF

100pF

100nF

100nF

100nF

100nF

OUTPUT SIGNAL

INPUT SIGNAL

LOS (output)

ISL35111