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DS1744 Datasheet(PDF) 3 Page - Maxim Integrated Products

Part # DS1744
Description  Y2K-Compliant, Nonvolatile Timekeeping RAMs
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Manufacturer  MAXIM [Maxim Integrated Products]
Direct Link  https://www.maximintegrated.com/en.html
Logo MAXIM - Maxim Integrated Products

DS1744 Datasheet(HTML) 3 Page - Maxim Integrated Products

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DS1744/DS1744P Y2K-Compliant, Nonvolatile Timekeeping RAMs
3 of 16
ORDERING INFORMATION
PART
VOLTAGE
(V)
TEMP RANGE
PIN-PACKAGE
TOP MARK**
DS1744-70+
5.0
0°C to +70°C
28 EDIP
DS1744+70
DS1744-70IND+
5.0
-40°C to +85°C
28 EDIP
DS1744+70 IND
DS1744W-120+
3.3
0°C to +70°C
28 EDIP
DS1744W+120
DS1744W-120IND+
3.3
-40°C to +85°C
28 EDIP
DS1744W+120 IND
DS1744P-70+
5.0
0°C to +70°C
34 PowerCap*
DS1744P+70
DS1744P-70IND+
5.0
-40°C to +85°C
34 PowerCap*
DS1744P+70 IND
DS1744WP-120+
3.3
0°C to +70°C
34 PowerCap*
DS1744WP+120
DS1744WP-120IND+
3.3
-40°C to +85°C
34 PowerCap*
DS1744WP+120 IND
+Denotes a lead(Pb)-free/RoHS-compliant package.
*DS9034-PCX+ or DS9034I-PCX+ required (must be ordered separately).
**A “+” anywhere in the top mark denotes a lead-free device. An “IND” denotes an industrial temperature grade device.
DESCRIPTION
The DS1744 is a full-function, year-2000-compliant (Y2KC), real-time clock/calendar (RTC) and 32k x 8
NV SRAM. User access to all registers within the DS1744 is accomplished with a byte-wide interface as
shown in Figure 1. The RTC information and control bits reside in the eight uppermost RAM locations.
The RTC registers contain century, year, month, date, day, hours, minutes, and seconds data in 24-hour
BCD format. Corrections for the date of each month and leap year are made automatically. The RTC clock
registers are double-buffered to avoid access of incorrect data that can occur during clock update cycles.
The double-buffered system also prevents time loss as the timekeeping countdown continues unabated by
access to time register data. The DS1744 also contains its own power-fail circuitry that deselects the
device when the VCC supply is in an out-of-tolerance condition. This feature prevents loss of data from
unpredictable system operation brought on by low VCC as errant access and update cycles are avoided.


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