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MAX16063 Datasheet(PDF) 11 Page - Maxim Integrated Products

Part # MAX16063
Description  1% Accurate, Low-Voltage, Quad Window Voltage Detector
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Manufacturer  MAXIM [Maxim Integrated Products]
Direct Link  https://www.maximintegrated.com/en.html
Logo MAXIM - Maxim Integrated Products

MAX16063 Datasheet(HTML) 11 Page - Maxim Integrated Products

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1% Accurate, Low-Voltage,
Quad Window Voltage Detector
______________________________________________________________________________________
11
RESET Output
RESET asserts low when the voltage on any of the
UVIN_ inputs falls below its respective threshold, the
voltage on any of the OVIN_ inputs goes above its
respective threshold, or MR is asserted. RESET
remains asserted for the reset timeout period after all
monitored UVIN_ inputs exceed their respective thresh-
olds, all OVIN_ inputs fall below their respective thresh-
olds, and MR is deasserted (see Figure 6). This
open-drain output has a 30µA internal pullup.
Reset Timeout Capacitor
The reset timeout period can be adjusted to accommo-
date a variety of microprocessor (µP) applications.
Adjust the reset timeout period (tRP) by connecting a
capacitor (CSRT) between SRT and GND. Calculate the
reset timeout capacitor as follows:
Connect SRT to VCC for a factory-programmed reset
timeout of 140ms (min).
Manual Reset Input (
MR)
Many µP-based products require manual reset capabil-
ity, allowing the operator, a test technician, or external
logic circuitry to initiate a reset. A logic-low on MR
asserts RESET low. RESET remains asserted while MR
is low, and during the reset timeout period (140ms min)
after MR returns high. The MR input has an internal
20k
Ω pullup resistor to VCC, so it can be left open if it is
not used. MR can be driven with TTL or CMOS-logic
levels, or with open-drain/collector outputs. Connect a
normally open momentary switch from MR to GND to
create a manual reset function; external debounce cir-
cuitry is not required. If MR is driven from long cables
or if the device is used in a noisy environment, connect-
ing a 0.1µF capacitor from MR to GND provides addi-
tional noise immunity.
CF
ts
V
I
SRT
RP
TH SRT
SRT
()
()
_
=
⎝⎜
⎠⎟
MAX16063
GND
VCC
GND
RESET
VCC
5V
UVOUT_
VCC = 3.3V
100k
Figure 5. Interfacing to a Different Logic Supply Voltage
UVIN_
10%
90%
10%
90%
RESET
UVOUT_
VTH_ + VTH_HYS
tRP
tD
tD
tRD
VTH_
OVIN_
VTH_ - VTH_HYS
VTH_
10%
90%
OVOUT_
tD
tD
Figure 6. Output Timing Diagram


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