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TDF8590TH Datasheet(PDF) 4 Page - NXP Semiconductors

Part # TDF8590TH
Description  2 X 80 W SE (4 OHM) or 1 X 160 W BTL (8 OHM) class-D amplifier
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

TDF8590TH Datasheet(HTML) 4 Page - NXP Semiconductors

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TDF8590TH_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 23 April 2007
4 of 30
NXP Semiconductors
TDF8590TH
2
× 80 W SE (4 Ω) or 1 × 160 W BTL (8 Ω) class-D amplifier
The TDF8590TH contains two independent amplifier channels with a differential input
stage, high output power, high efficiency (90 %), low distortion and a low quiescent
current. The amplifier channels can be connected in the following configurations:
Mono Bridge-Tied Load (BTL) amplifier
Dual Single-Ended (SE) amplifiers
The TDF8590TH also contains circuits common to both channels such as the oscillator, all
reference sources, the mode functionality and a digital timing manager. For protection a
thermal foldback, temperature, current and voltage protection are built in.
6.2 Mode selection
The TDF8590TH can be switched in three operating modes via pin MODE:
Standby mode; the amplifiers are switched off to achieve a very low supply current
Mute mode; the amplifiers are switching idle (50 % duty cycle), but the audio signal at
the output is suppressed by disabling the VI-converter input stages
Operating mode; the amplifiers are fully operational with output signal
The input stage (see Figure 1) contributes to the DC offset measured at the amplifier
output. To avoid pop noise the DC output offset voltage should be increased gradually at a
mode transition from mute to operating, or vice versa, by limiting the dVMODE/dt on pin
MODE, resulting in a small dVO(offset)/dt for the DC output offset voltage. The required time
constant for a gradually increase of the DC output offset voltage between mute and
operating is generated via an RC network on pin MODE. An example of a switching circuit
for driving pin MODE is illustrated in Figure 3 and explained in Table 3.
Fig 3.
Example of mode selection circuit
Table 3.
Mode selection
S1
S2
Mode selection
closed
closed
Standby mode
closed
open
Standby mode
open
closed
Mute mode
open
open
Operating mode
001aad836
5.6 k
5.6 k
5.6 V
5.6 k
S1
S2
MODE
SGND
100
µF
(10 V)
VDDP


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