ADN2526

Rev. A | Page 10 of 16

THEORY OF OPERATION

As shown in Figure 1, the ADN2526 consists of an input stage

and two voltage-controlled current sources for bias and modula-

tion. The bias current, which is available at the IBIAS pin, is

controlled by the voltage applied at the BSET pin and can be

monitored at the IBMON pin. The differential modulation

current, which is available at the IMODP and IMODN pins, is

controlled by the voltage applied to the MSET pin. The output

stage implements the active back-match circuitry for proper

transmission line matching and power consumption reduction.

The ADN2526 can drive a load having differential resistance

ranging from 5 Ω to 50 Ω. The excellent back-termination in

the ADN2526 absorbs the signal reflections from the TOSA

end, enabling excellent optical eye quality, even though the

TOSA is significantly misterminated.

INPUT STAGE

The input stage of the ADN2526 converts the data signal applied

to the DATAP and DATAN pins to a level that ensures proper

operation of the high speed switch. The equivalent circuit of the

input stage is shown in Figure 17.

VCC

50Ω

50Ω

VCC

DATAP

DATAN

Figure 17. Equivalent Circuit of the Input Stage

The DATAP and DATAN pins are terminated internally with a

100 Ω differential termination resistor. This minimizes signal

reflections at the input, which can otherwise lead to degradation in

the output eye diagram. It is not recommended to drive the

ADN2526 with single-ended data signal sources.

The ADN2526 input stage must be ac-coupled to the signal

source to eliminate the need for matching between the common-

mode voltages of the data signal source and the input stage of

the driver (see Figure 18). The ac-coupling capacitors should

have an impedance much less than 50 Ω over the required

frequency range. Generally, this is achieved using 10 nF to 100 nF

capacitors.

In SFP+ MSA applications, the DATAP and DATAN pins need

to be connected to the SFP+ connector directly. This connection

requires enhanced ESD protection to support the SFP+ module

hot plug-in application.

ADN2526

DATAP

DATAN

C

C

50Ω

50Ω

DATA SIGNAL SOURCE

Figure 18. AC-Coupling the Data Source to the ADN2526 Data Inputs

BIAS CURRENT

The bias current is generated internally using a voltage-to-current

converter consisting of an internal operational amplifier and a

transistor, as shown in Figure 19.

GND

200Ω

800Ω

2Ω

RR

VCC

IBMON

BSET

ADN2526

200Ω

IBIAS

Figure 19. Voltage-to-Current Converter Used to Generate IBIAS

The voltage-to-current conversion factor is set at 100 mA/V by

the internal resistors, and the bias current is monitored using a

current mirror with a gain equal to 1/100. By connecting a 1 kΩ

resistor between IBMON and VEE, the bias current can be moni-

tored as a voltage across the resistor. A low temperature coefficient

in its value over temperature contributes to the overall error

budget for the IBIAS monitor voltage. If the IBMON voltage is

should be placed close to the ADC to minimize errors due to

voltage drops on the ground plane.

The equivalent circuits of the BSET, IBIAS, and IBMON pins

are shown in Figure 20, Figure 21, and Figure 22.

VCC

BSET

VCC

800Ω

200Ω

Figure 20. Equivalent Circuit of the BSET Pin