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T9300 Datasheet(PDF) 8 Page - Intel Corporation |
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T9300 Datasheet(HTML) 8 Page - Intel Corporation |
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8 / 77 page  Introduction 8 Datasheet 1.1 Terminology Term Definition # A “#” symbol after a signal name refers to an active low signal, indicating a signal is in the active state when driven to a low level. For example, when RESET# is low, a reset has been requested. Conversely, when NMI is high, a nonmaskable interrupt has occurred. In the case of signals where the name does not imply an active state but describes part of a binary sequence (such as address or data), the “#” symbol implies that the signal is inverted. For example, D[3:0] = “HLHL” refers to a hex ‘A’, and D[3:0]# = “LHLH” also refers to a hex “A” (H= High logic level, L= Low logic level). AGTL+ Advanced Gunning Transceiver Logic. Used to refer to Assisted GTL+ signaling technology on some Intel® processors. Enhanced Intel SpeedStep® Technology Technology that provides power management capabilities to laptops. Execute Disable Bit The Execute Disable bit allows memory to be marked as executable or non- executable, when combined with a supporting operating system. If code attempts to run in non-executable memory the processor raises an error to the operating system. This feature can prevent some classes of viruses or worms that exploit buffer overrun vulnerabilities and can thus help improve the overall security of the system. See the Intel® Architecture Software Developer's Manual for more detailed information. Front Side Bus (FSB) Refers to the interface between the processor and system core logic (also known as the chipset components). Half ratio support (N/2) for Core to Bus ratio Penryn processor support the N/2 feature which allows having fractional core to bus ratios. This feature provides the flexibility of having more frequency options and be able to have products with smaller frequency steps. Intel® 64 Technology 64-bit memory extensions to the IA-32 architecture. Intel® Virtualization Technology Processor virtualization which, when used in conjunction with Virtual Machine Monitor software enables multiple, robust independent software environments inside a single platform. Processor Core Processor core die with integrated L1 and L2 cache. All AC timing and signal integrity specifications are at the pads of the processor core. Storage Conditions Refers to a non-operational state. The processor may be installed in a platform, in a tray, or loose. Processors may be sealed in packaging or exposed to free air. Under these conditions, processor landings should not be connected to any supply voltages, have any I/Os biased or receive any clocks. Upon exposure to “free air” (i.e., unsealed packaging or a device removed from packaging material) the processor must be handled in accordance with moisture sensitivity labeling (MSL) as indicated on the packaging material. TDP Thermal Design Power. VCC The processor core power supply. VSS The processor ground. |
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