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C8051F50X Datasheet(PDF) 46 Page - Silicon Laboratories

Part # C8051F50X
Description  Mixed Signal ISP Flash MCU Family
Download  312 Pages
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Manufacturer  SILABS [Silicon Laboratories]
Direct Link  http://www.silabs.com
Logo SILABS - Silicon Laboratories

C8051F50X Datasheet(HTML) 46 Page - Silicon Laboratories

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C8051F50x-F51x
46
Rev. 1.1
Table 5.4. Reset Electrical Characteristics
–40 to +125 °C unless otherwise specified.
Parameter
Conditions
Min
Typ
Max
Units
RST Output Low Voltage
VIO = 5 V; IOL = 70 µA
40
mV
RST Input High Voltage
0.7 x VIO
——
RST Input Low Voltage
0.3 x VIO
RST Input Pullup Current
RST = 0.0 V, VIO = 5 V
47
115
µA
VDD RST Threshold (VRST-LOW)
1.65
1.75
1.80
V
VDD RST Threshold (VRST-HIGH)
2.25
2.30
2.45
V
Missing Clock Detector Timeout
Time from last system clock
rising edge to reset initiation
VDD = 2.1V
VDD = 2.5V
200
200
370
270
600
600
µs
Reset Time Delay
Delay between release of
any reset source and code
execution at location 0x0000
—130
160
µs
Minimum RST Low Time to
Generate a System Reset
6—
µs
VDD Monitor Turn-on Time
—60
100
µs
VDD Monitor Supply Current
—1
2
µA
Table 5.5. Flash Electrical Characteristics
VDD = 1.8 to 2.75 V, –40 to +125 °C unless otherwise specified.
Parameter
Conditions
Min
Typ
Max
Units
Flash Size
C8051F500/1/2/3/8/9
65536*
Bytes
C8051F504/5/6/7-F510/1
32768
Endurance
20 k
150 k
Erase/Write
Flash Retention
85 °C
10
Years
Erase Cycle Time
25 MHz System Clock
28
30
45
ms
Write Cycle Time
25 MHz System Clock
79
84
125
µs
VDD
Write / Erase operations
VRST-HIGH
2
——
V
1.
On the 64K Flash devices, 1024 bytes at addresses 0xFC00 to 0xFFFF are reserved.
2.
See Table 5.4 for the
VRST-HIGH specification.


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