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C8051F50X Datasheet(PDF) 62 Page - Silicon Laboratories |
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C8051F50X Datasheet(HTML) 62 Page - Silicon Laboratories |
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62 / 312 page  C8051F50x-F51x 62 Rev. 1.1 Indirect Address = 0x08; Gain Register Definition 6.3. ADC0GNA: ADC0 Additional Selectable Gain Bit 7 6 5 4 3 2 1 0 Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved GAINADD Type W W W W W W W W Reset 0 0 0 0 0 0 0 1 Bit Name Function 7:1 Reserved Must Write 0000000b. 0 GAINADD ADC0 Additional Gain Bit. Setting this bit add 1/64 (0.016) gain to the gain value in the ADC0GNH and ADC0GNL registers. Note : This register is accessed indirectly; See Section 6.3.2 for details for writing this register. |
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