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C8051F50X Datasheet(PDF) 66 Page - Silicon Laboratories

Part # C8051F50X
Description  Mixed Signal ISP Flash MCU Family
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Manufacturer  SILABS [Silicon Laboratories]
Direct Link  http://www.silabs.com
Logo SILABS - Silicon Laboratories

C8051F50X Datasheet(HTML) 66 Page - Silicon Laboratories

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C8051F50x-F51x
66
Rev. 1.1
SFR Address = 0xBA; SFR Page = 0x00;
6.4. Programmable Window Detector
The ADC Programmable Window Detector continuously compares the ADC0 output registers to user-pro-
grammed limits, and notifies the system when a desired condition is detected. This is especially effective in
an interrupt-driven system, saving code space and CPU bandwidth while delivering faster system
response times. The window detector interrupt flag (AD0WINT in register ADC0CN) can also be used in
polled mode. The ADC0 Greater-Than (ADC0GTH, ADC0GTL) and Less-Than (ADC0LTH, ADC0LTL)
registers hold the comparison values. The window detector flag can be programmed to indicate when mea-
sured data is inside or outside of the user-programmed limits, depending on the contents of the ADC0
Less-Than and ADC0 Greater-Than registers.
SFR Definition 6.8. ADC0TK: ADC0 Tracking Mode Select
Bit
7
6
5
4
3
2
1
0
Name
AD0PWR[3:0]
AD0TM[1:0]
AD0TK[1:0]
Type
R/W
R/W
R/W
Reset
1
1
1
1
1
1
1
1
Bit
Name
Function
7:4
AD0PWR[3:0] ADC0 Burst Power-Up Time.
For BURSTEN = 0: ADC0 Power state controlled by AD0EN
For BURSTEN = 1, AD0EN = 1: ADC0 remains enabled and does not enter the
very low power state
For BURSTEN = 1, AD0EN = 0: ADC0 enters the very low power state and is
enabled after each convert start signal. The Power-Up time is programmed accord-
ing the following equation:
or
3:2
AD0TM[1:0]
ADC0 Tracking Mode Enable Select Bits.
00: Reserved.
01: ADC0 is configured to Post-Tracking Mode.
10: ADC0 is configured to Pre-Tracking Mode.
11: ADC0 is configured to Dual Tracking Mode.
1:0
AD0TK[1:0]
ADC0 Post-Track Time.
00: Post-Tracking time is equal to 2 SAR clock cycles + 2 FCLK cycles.
01: Post-Tracking time is equal to 4 SAR clock cycles + 2 FCLK cycles.
10: Post-Tracking time is equal to 8 SAR clock cycles + 2 FCLK cycles.
11: Post-Tracking time is equal to 16 SAR clock cycles + 2 FCLK cycles.
AD0PWR
Tstartup
200ns
------------------------
1
=
Tstartup
AD0PWR
1
+
200ns
=


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