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C8051F50X Datasheet(PDF) 74 Page - Silicon Laboratories

Part # C8051F50X
Description  Mixed Signal ISP Flash MCU Family
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Manufacturer  SILABS [Silicon Laboratories]
Direct Link  http://www.silabs.com
Logo SILABS - Silicon Laboratories

C8051F50X Datasheet(HTML) 74 Page - Silicon Laboratories

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C8051F50x-F51x
74
Rev. 1.1
SFR Address = 0xD1; SFR Page = 0x00
SFR Definition 8.1. REF0CN: Reference Control
Bit
7
6
5
4
3
2
1
0
Name
ZTCEN
REFLV
REFSL
TEMPE
BIASE
REFBE
Type
R
R
R
R
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
Name
Function
7:6
Unused
Read = 00b; Write = don’t care.
5
ZTCEN
Zero Temperature Coefficient Bias Enable Bit.
0: ZeroTC Bias Generator automatically enabled when required.
1: ZeroTC Bias Generator forced on.
4
REFLV
Voltage Reference Output Level Select.
This bit selects the output voltage level for the internal voltage reference
0: Internal voltage reference set to 1.5 V.
1: Internal voltage reference set to 2.20 V.
3
REFSL
Voltage Reference Select.
This bit selects the ADCs voltage reference.
0: VREF pin used as voltage reference.
1: VDD used as voltage reference.
2
TEMPE
Temperature Sensor Enable Bit.
0: Internal Temperature Sensor off.
1: Internal Temperature Sensor on.
1
BIASE
Internal Analog Bias Generator Enable Bit.
0: Internal Bias Generator off.
1: Internal Bias Generator on.
0
REFBE
On-chip Reference Buffer Enable Bit.
0: On-chip Reference Buffer off.
1: On-chip Reference Buffer on. Internal voltage reference driven on the VREF pin.


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