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C8051F50X Datasheet(PDF) 95 Page - Silicon Laboratories |
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C8051F50X Datasheet(HTML) 95 Page - Silicon Laboratories |
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95 / 312 page  Rev. 1.1 95 C8051F50x-F51x SFR Address = 0xD0; SFR Page = All Pages; Bit-Addressable SFR Definition 11.6. PSW: Program Status Word Bit 7 6 5 4 3 2 1 0 Name CY AC F0 RS[1:0] OV F1 PARITY Type R/W R/W R/W R/W R/W R/W R Reset 0 0 0 0 0 0 0 0 Bit Name Function 7 CY Carry Flag. This bit is set when the last arithmetic operation resulted in a carry (addition) or a bor- row (subtraction). It is cleared to logic 0 by all other arithmetic operations. 6 AC Auxiliary Carry Flag. This bit is set when the last arithmetic operation resulted in a carry into (addition) or a borrow from (subtraction) the high order nibble. It is cleared to logic 0 by all other arith- metic operations. 5 F0 User Flag 0. This is a bit-addressable, general purpose flag for use under software control. 4:3 RS[1:0] Register Bank Select. These bits select which register bank is used during register accesses. 00: Bank 0, Addresses 0x00-0x07 01: Bank 1, Addresses 0x08-0x0F 10: Bank 2, Addresses 0x10-0x17 11: Bank 3, Addresses 0x18-0x1F 2 OV Overflow Flag. This bit is set to 1 under the following circumstances: An ADD, ADDC, or SUBB instruction causes a sign-change overflow. A MUL instruction results in an overflow (result is greater than 255). A DIV instruction causes a divide-by-zero condition. The OV bit is cleared to 0 by the ADD, ADDC, SUBB, MUL, and DIV instructions in all other cases. 1 F1 User Flag 1. This is a bit-addressable, general purpose flag for use under software control. 0 PARITY Parity Flag. This bit is set to logic 1 if the sum of the eight bits in the accumulator is odd and cleared if the sum is even. |
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