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C8051F50X Datasheet(PDF) 17 Page - Silicon Laboratories

Part # C8051F50X
Description  Mixed Signal ISP Flash MCU Family
Download  312 Pages
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Manufacturer  SILABS [Silicon Laboratories]
Direct Link  http://www.silabs.com
Logo SILABS - Silicon Laboratories

C8051F50X Datasheet(HTML) 17 Page - Silicon Laboratories

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Rev. 1.1
17
C8051F50x-F51x
Figure 1.1. C8051F500/1/4/5 Block Diagram
Digital Peripherals
UART0
Timers 0,
1, 2, 3
PCA
WDT
LIN 2.1
Priority
Crossbar
Decoder
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
Crossbar Control
Port I/O Configuration
SFR
Bus
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
SPI
Debug /
Programming
Hardware
Power On
Reset
Reset
C2D
C2CK/RST
P1.6
P1.7
Analog Peripherals
Comparator 0
+
-
12-bit
200ksps
ADC
A
M
U
X
VREF
VDD
VDD
VREF
GND
CP0, CP0A
Voltage
Reference
VREF
System Clock Setup
External Oscillator
XTAL1
CIP-51 8051
Controller Core
up to 64kB Byte Flash
Program Memory
256 Byte RAM
Port 0
Drivers
Port 1
Drivers
Voltage Regulator
(LDO)
GND
VREGIN
VDD
XTAL2
VIO
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
Port 2
Drivers
Port 3
Drivers
P4.0
P4.1
P4.2
P4.3
P4.4
P4.5
P4.6
P4.7
Port 4
Drivers
Temp
Sensor
P0 – P3
Comparator 1
+
-
CP1, CP1A
CAN 2.0B
GNDA
VDDA
Clock Multiplier
Internal Oscillator
External Memory Interface
4 kB XRAM
*On F500/4 Devices
I2C


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