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C8051F50X Datasheet(PDF) 34 Page - Silicon Laboratories |
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C8051F50X Datasheet(HTML) 34 Page - Silicon Laboratories |
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34 / 312 page  C8051F50x-F51x 34 Rev. 1.1 4.3. QFN-40 Package Specifications Figure 4.5. Typical QFN-40 Package Drawing Table 4.5. QFN-40 Package Dimensions Dimension Min Typ Max Dimension Min Typ Max A 0.80 0.85 0.90 E2 4.00 4.10 4.20 A1 0.00 0.05 L 0.35 0.40 0.45 b 0.18 0.23 0.28 L1 0.10 D 6.00 BSC aaa 0.10 D2 4.00 4.10 4.20 bbb 0.10 e 0.50 BSC ddd 0.05 E 6.00 BSC eee 0.08 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to JEDEC Solid State Outline MO-220, variation VJJD-5, except for features A, D2, and E2 which are toleranced per supplier designation. 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. |
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